Joris van Rantwijk 22e481f3e6 * Add trivial top-level designs for synthesis dry-run.		2016-04-18 22:57:41 +02:00
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top_d18_p20.vhdl	* Add trivial top-level designs for synthesis dry-run.	2016-04-18 22:57:41 +02:00
top_d24_p26.vhdl	* Add trivial top-level designs for synthesis dry-run.	2016-04-18 22:57:41 +02:00