vhdl-sincos-gen/synth
Joris van Rantwijk 22e481f3e6 * Add trivial top-level designs for synthesis dry-run. 2016-04-18 22:57:41 +02:00
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xilinx_spartan6 * Add trivial top-level designs for synthesis dry-run. 2016-04-18 22:57:41 +02:00