Sine/cosine function core in VHDL
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Joris van Rantwijk 0685db9d92 Document latency of sincos core. 2016-04-10 01:27:24 +02:00
rtl Document latency of sincos core. 2016-04-10 01:27:24 +02:00
sim Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-10 01:26:05 +02:00