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vhdl-sincos-gen
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e1d1e4cb09
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Joris van Rantwijk
e1d1e4cb09
* Fix missing type conversions in top-level synthesis files.
2016-04-18 23:37:23 +02:00
Joris van Rantwijk
22e481f3e6
* Add trivial top-level designs for synthesis dry-run.
2016-04-18 22:57:41 +02:00