joris
/
vhdl-sincos-gen
1
0
Fork 0
Code Issues Pull Requests Activity
36 Commits 1 Branch 0 Tags 89 KiB
Commit Graph

3 Commits

Author SHA1 Message Date
Joris van Rantwijk 8719b47c6f Finish synthesizable test design. 
Finish implementation of test_sincos_serial.
It has not been tested at all yet.
 2016-04-20 23:42:30 +02:00
Joris van Rantwijk 5e02c373de * Implement serial port interface in test design. 2016-04-18 21:14:31 +02:00
Joris van Rantwijk 5b72e7f3f3 * Start work on synthesizable tester for sin/cos core. 2016-04-16 22:56:42 +02:00