Joris van Rantwijk
331211f34b
Fix bugs in test_sincos_serial.vhdl.
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* Allow choice of core at run-time instead of synthesis-time.
* Fix mistake in serial port RX machine.
2016-04-21 22:20:32 +02:00
Joris van Rantwijk
84c92fea95
Fix analysis errors in test_sincos_serial.vhdl.
2016-04-21 20:36:11 +02:00
Joris van Rantwijk
fe5dfa9133
Fix mistakes in changes related to phase_extrabits.
2016-04-20 23:46:42 +02:00
Joris van Rantwijk
ba096abf16
Make internal phase accuracy configurable.
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* Add generic "phase_extrabits" to set internal accuracy of phase remainder.
* Increase default value of phase_extrabits from 1 to 2.
2016-04-20 23:46:24 +02:00
Joris van Rantwijk
8719b47c6f
Finish synthesizable test design.
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Finish implementation of test_sincos_serial.
It has not been tested at all yet.
2016-04-20 23:42:30 +02:00
385c9f5ed2
* Finally found a way to describe the lookup table such that both
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ISE and Vivado infer a dual-port block RAM.
2016-04-19 23:36:10 +02:00
2ed074011e
* Change description of lookup table to force inference of ROM block
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on Virtex-7 with Vivado.
2016-04-19 23:36:10 +02:00
Joris van Rantwijk
5e02c373de
* Implement serial port interface in test design.
2016-04-18 21:14:31 +02:00
Joris van Rantwijk
5b72e7f3f3
* Start work on synthesizable tester for sin/cos core.
2016-04-16 22:56:42 +02:00
Joris van Rantwijk
5892955445
* Reorganize comments at top of wrappers for sin/cos generator.
2016-04-16 22:16:20 +02:00
Joris van Rantwijk
8796491f37
* Further reduction of multiplier width.
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At this point it very slightly affects output quality.
This change makes it possible to implement up to 24-bit sine generators
using just 18x18-bit multipliers (i.e. Spartan-6).
2016-04-16 09:10:27 +02:00
Joris van Rantwijk
d2a948f34e
* Fix mistake in 2nd order Taylor correction.
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* Fix mistake in testbench for 24-bit sine generator.
2016-04-14 23:14:58 +02:00
Joris van Rantwijk
42046dc818
* Add wrapper for 24-bit sine generator.
2016-04-14 22:53:40 +02:00
Joris van Rantwijk
9873f91e8e
* Further reduction of multiplier width.
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* Add more comments.
2016-04-14 22:49:32 +02:00
Joris van Rantwijk
a3d8939440
* Add comments.
2016-04-14 00:42:58 +02:00
Joris van Rantwijk
2dbc6d44db
* Reduce width of sin/cos input to multiplier by 1 bit.
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* This has no significant effect on accuracy, but reduces multiplier width.
2016-04-14 00:05:52 +02:00
Joris van Rantwijk
9f4bb7f9b0
* Increase precision of delta_phase term by 1 bit.
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* This improves accuracy of 1st order Taylor variant to less than 1.0 lsb peak deviation.
* Add comments.
2016-04-13 23:32:02 +02:00
Joris van Rantwijk
12b896c2df
Fix mistake in Taylor correction.
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This improves accuracy, but there is probably room for further improvement by avoiding accumulation of rounding errors.
2016-04-11 23:21:25 +02:00
Joris van Rantwijk
7de76c6696
Reduce amplitude to avoid numeric overflow.
2016-04-11 21:28:17 +02:00
Joris van Rantwijk
0685db9d92
Document latency of sincos core.
2016-04-10 01:27:24 +02:00
Joris van Rantwijk
8090886ab0
VHDL wrapper for sin/cos function with 18-bit sin/cos, 20-bit phase.
2016-03-24 23:34:20 +01:00
Joris van Rantwijk
59ec0505ab
Main VHDL file of sin/cos function core.
2016-03-24 23:32:59 +01:00
Joris van Rantwijk
Joris van Rantwijk