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vhdl-sincos-gen
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2 Commits

Author SHA1 Message Date
Joris van Rantwijk d2a948f34e * Fix mistake in 2nd order Taylor correction. 
* Fix mistake in testbench for 24-bit sine generator.
 2016-04-14 23:14:58 +02:00
Joris van Rantwijk 15518ce6f7 * Add test-bench for superficial check of 24-bit sine generator. 
* Minor improvement in test-bench for 18-bit sine generator.
 2016-04-14 23:06:21 +02:00