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* Fix missing type conversions in top-level synthesis files.

This commit is contained in:
Joris van Rantwijk 2016-04-18 23:37:23 +02:00
parent 22e481f3e6
commit e1d1e4cb09
2 changed files with 6 additions and 6 deletions
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6
synth/xilinx_spartan6/top_d18_p20.vhdl
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@ -36,9 +36,9 @@ begin
process (clk) is process (clk) is
begin begin
if rising_edge(clk) then if rising_edge(clk) then
r_in_phase <= in_phase; r_in_phase <= unsigned(in_phase);
out_sin <= s_out_sin; out_sin <= std_logic_vector(s_out_sin);
out_cos <= s_out_cos; out_cos <= std_logic_vector(s_out_cos);
end if; end if;
end process; end process;

6
synth/xilinx_spartan6/top_d24_p26.vhdl
View File

@ -36,9 +36,9 @@ begin
process (clk) is process (clk) is
begin begin
if rising_edge(clk) then if rising_edge(clk) then
r_in_phase <= in_phase; r_in_phase <= unsigned(in_phase);
out_sin <= s_out_sin; out_sin <= std_logic_vector(s_out_sin);
out_cos <= s_out_cos; out_cos <= std_logic_vector(s_out_cos);
end if; end if;
end process; end process;