From e1d1e4cb09796f122b90e6a184b29d52e3ff131a Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Mon, 18 Apr 2016 23:37:23 +0200 Subject: [PATCH] * Fix missing type conversions in top-level synthesis files. --- synth/xilinx_spartan6/top_d18_p20.vhdl | 6 +++--- synth/xilinx_spartan6/top_d24_p26.vhdl | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/synth/xilinx_spartan6/top_d18_p20.vhdl b/synth/xilinx_spartan6/top_d18_p20.vhdl index 46e7553..2af32f7 100644 --- a/synth/xilinx_spartan6/top_d18_p20.vhdl +++ b/synth/xilinx_spartan6/top_d18_p20.vhdl @@ -36,9 +36,9 @@ begin process (clk) is begin if rising_edge(clk) then - r_in_phase <= in_phase; - out_sin <= s_out_sin; - out_cos <= s_out_cos; + r_in_phase <= unsigned(in_phase); + out_sin <= std_logic_vector(s_out_sin); + out_cos <= std_logic_vector(s_out_cos); end if; end process; diff --git a/synth/xilinx_spartan6/top_d24_p26.vhdl b/synth/xilinx_spartan6/top_d24_p26.vhdl index 24149ef..a064243 100644 --- a/synth/xilinx_spartan6/top_d24_p26.vhdl +++ b/synth/xilinx_spartan6/top_d24_p26.vhdl @@ -36,9 +36,9 @@ begin process (clk) is begin if rising_edge(clk) then - r_in_phase <= in_phase; - out_sin <= s_out_sin; - out_cos <= s_out_cos; + r_in_phase <= unsigned(in_phase); + out_sin <= std_logic_vector(s_out_sin); + out_cos <= std_logic_vector(s_out_cos); end if; end process;