joris
/
vhdl-sincos-gen
1
0
Fork 0
Code Issues Pull Requests Activity

* Reorganize comments at top of wrappers for sin/cos generator.

This commit is contained in:
Joris van Rantwijk 2016-04-16 22:16:20 +02:00
parent 8796491f37
commit 5892955445
2 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
rtl/sincos_gen_d18_p20.vhdl
View File

@ -1,5 +1,11 @@
-- --
-- Sine / cosine function core -- Wrapper for sine / cosine function core
--
-- Copyright 2016 Joris van Rantwijk
--
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- --
-- Phase input: -- Phase input:
-- unsigned 20 bits (2**20 steps for a full circle) -- unsigned 20 bits (2**20 steps for a full circle)
@ -10,13 +16,6 @@
-- Latency: -- Latency:
-- 6 clock cycles -- 6 clock cycles
-- --
-- Copyright 2016 Joris van Rantwijk
--
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;

17
rtl/sincos_gen_d24_p26.vhdl
View File

@ -1,5 +1,13 @@
-- --
-- Sine / cosine function core -- Wrapper for sine / cosine function core
--
-- Copyright 2016 Joris van Rantwijk
--
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- --
-- Phase input: -- Phase input:
-- unsigned 26 bits (2**26 steps for a full circle) -- unsigned 26 bits (2**26 steps for a full circle)
@ -10,13 +18,6 @@
-- Latency: -- Latency:
-- 9 clock cycles -- 9 clock cycles
-- --
-- Copyright 2016 Joris van Rantwijk
--
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;