From 589295544556d0c3b04a7ca3bd921629cfa7bafd Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Sat, 16 Apr 2016 22:16:20 +0200 Subject: [PATCH] * Reorganize comments at top of wrappers for sin/cos generator. --- rtl/sincos_gen_d18_p20.vhdl | 15 +++++++-------- rtl/sincos_gen_d24_p26.vhdl | 17 +++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/rtl/sincos_gen_d18_p20.vhdl b/rtl/sincos_gen_d18_p20.vhdl index 1754d80..fe970eb 100644 --- a/rtl/sincos_gen_d18_p20.vhdl +++ b/rtl/sincos_gen_d18_p20.vhdl @@ -1,5 +1,11 @@ -- --- Sine / cosine function core +-- Wrapper for sine / cosine function core +-- +-- Copyright 2016 Joris van Rantwijk +-- +-- This design is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either -- -- Phase input: -- unsigned 20 bits (2**20 steps for a full circle) @@ -10,13 +16,6 @@ -- Latency: -- 6 clock cycles -- --- Copyright 2016 Joris van Rantwijk --- --- This design is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- library ieee; use ieee.std_logic_1164.all; diff --git a/rtl/sincos_gen_d24_p26.vhdl b/rtl/sincos_gen_d24_p26.vhdl index f73a75f..3c2e5d3 100644 --- a/rtl/sincos_gen_d24_p26.vhdl +++ b/rtl/sincos_gen_d24_p26.vhdl @@ -1,5 +1,13 @@ -- --- Sine / cosine function core +-- Wrapper for sine / cosine function core +-- +-- Copyright 2016 Joris van Rantwijk +-- +-- This design is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. +-- -- -- Phase input: -- unsigned 26 bits (2**26 steps for a full circle) @@ -10,13 +18,6 @@ -- Latency: -- 9 clock cycles -- --- Copyright 2016 Joris van Rantwijk --- --- This design is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- library ieee; use ieee.std_logic_1164.all;