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vhdl-sincos-gen
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Fix mistake in Taylor correction. 

This improves accuracy, but there is probably room for further improvement by avoiding accumulation of rounding errors.
This commit is contained in:
Joris van Rantwijk 2016-04-11 23:21:25 +02:00
parent 7de76c6696
commit 12b896c2df
1 changed files with 2 additions and 2 deletions
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rtl/sincos_gen.vhdl
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@ -192,8 +192,8 @@ begin
-- Keep phase remainder and work on multiplication by Pi/2.
r2_rphase <= r1_rphase;
r2_dphase <= r1_dphase +
resize(r1_dphase(dphase_bits-1 downto 6), dphase_bits) +
signed("0" & r1_dphase(5 downto 5));
resize(r1_dphase(dphase_bits-1 downto 7), dphase_bits) +
signed("0" & r1_dphase(6 downto 6));
-- Table lookup.
r2_sin_data <= unsigned(lookup_table(to_integer(r1_sin_addr)));