419 lines
14 KiB
VHDL
419 lines
14 KiB
VHDL
--
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-- Synthesizable design for testing the sine / cosine function core.
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--
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-- Copyright 2016 Joris van Rantwijk
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--
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-- This design is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity test_sincos_serial is
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generic (
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-- Clock frequency divider from system clock to serial bitrate.
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-- bitrate = system_clock_frequency / serial_bitrate_divider
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serial_bitrate_divider: integer range 10 to 8192;
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-- Select core.
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-- 1 = 18-bit sin/cos generator;
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-- 2 = 24-bit sin/cos generator.
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core_select: integer range 1 to 2 );
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port (
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-- System clock, active on rising edge.
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clk: in std_logic;
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-- Synchronous reset, active high.
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rst: in std_logic;
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-- Serial RX input.
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ser_rx: in std_logic;
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-- Serial TX output.
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ser_tx: out std_logic );
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end entity;
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architecture rtl of test_sincos_serial is
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constant latency: integer := 3 + 3 * core_select;
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signal r_clk_en: std_logic;
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signal r_in_phase: unsigned(31 downto 0);
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signal s_out_sin: signed(31 downto 0);
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signal s_out_cos: signed(31 downto 0);
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signal s_gen1_out_sin: signed(17 downto 0);
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signal s_gen1_out_cos: signed(17 downto 0);
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signal s_gen2_out_sin: signed(23 downto 0);
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signal s_gen2_out_cos: signed(23 downto 0);
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signal r_tst_start: std_logic;
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signal r_tst_in_phase: unsigned(31 downto 0);
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signal r_tst_out_sin: unsigned(31 downto 0);
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signal r_tst_out_cos: unsigned(31 downto 0);
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signal r_tst_busy: std_logic;
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signal r_tst_cyclecnt: unsigned(3 downto 0);
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signal r_clkmod: std_logic;
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signal r_clkmod_cnt: unsigned(3 downto 0);
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signal r_clkmod_tmp: std_logic;
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signal r_ctl_state: std_logic_vector(3 downto 0);
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signal r_ser_rx_strobe: std_logic;
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signal r_ser_rx_byte: std_logic_vector(7 downto 0);
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signal r_ser_rx_glitch: std_logic_vector(7 downto 0);
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signal r_ser_rx_bit: std_logic;
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signal r_ser_rx_timer: unsigned(12 downto 0);
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signal r_ser_rx_timeout: std_logic;
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signal r_ser_rx_state; std_logic_vector(1 downto 0);
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signal r_ser_rx_shift: std_logic_vector(8 downto 0);
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signal r_ser_tx_strobe: std_logic;
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signal r_ser_tx_busy: std_logic;
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signal r_ser_tx_byte: std_logic_vector(7 downto 0);
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signal r_ser_tx_bit: std_logic;
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signal r_ser_tx_timer: unsigned(12 downto 0);
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signal r_ser_tx_timeout: std_logic;
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signal r_ser_tx_bitcnt: unsigned(3 downto 0);
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signal r_ser_tx_shift: std_logic_vector(7 downto 0);
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begin
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-- Instantiate 18-bit sin/cos core.
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gen1: if core_select = 1 generate
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gen1x: entity work.sincos_gen_d18_p20
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port map (
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clk => clk,
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clk_en => r_clk_en,
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in_phase => r_in_phase(19 downto 0),
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out_sin => s_gen1_out_sin,
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out_cos => s_gen1_out_cos );
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s_out_sin <= resize(s_gen1_out_sin, 32);
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s_out_cos <= resize(s_gen1_out_cos, 32);
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end generate;
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-- Instantiate 24-bit sin/cos core.
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gen2: if core_select = 2 generate
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gen2x: entity work.sincos_gen_d24_p26
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port map (
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clk => clk,
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clk_en => r_clk_en,
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in_phase => r_in_phase(25 downto 0),
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out_sin => s_gen2_out_sin,
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out_cos => s_gen2_out_cos );
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s_out_sin <= resize(s_gen2_out_sin, 32);
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s_out_cos <= resize(s_gen2_out_cos, 32);
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end generate;
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-- Synchronous process.
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-- State machine for interface to design under test.
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process (clk) is
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begin
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if rising_edge(clk) then
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if r_clk_en = '1' then
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r_tst_cyclecnt <= r_tst_cyclecnt + 1;
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r_in_phase <= (others => '0');
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end if;
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if r_tst_busy = '1' and r_tst_cyclecnt = latency then
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r_tst_busy <= '0';
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r_tst_out_sin <= s_out_sin;
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r_tst_out_cos <= s_out_cos;
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end if;
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if r_tst_start = '1' and r_tst_busy = '0' then
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r_tst_busy <= '1';
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r_in_phase <= r_tst_in_phase;
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r_tst_cyclecnt <= (others => '0');
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end if;
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if rst = '1' then
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r_tst_busy <= '0';
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end if;
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end if;
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end process;
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-- Synchronous process.
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-- Drive clk_en signal (continuous or modulated).
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process (clk) is
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begin
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if rising_edge(clk) then
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if r_clkmod = '0' then
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-- Clock-enable modulation disabled.
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r_clk_en <= '1';
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else
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-- Clock-enable modulation active.
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r_clk_en <= r_clkmod_tmp;
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end if;
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-- Make r_clkmod_tmp high on 5 out of 16 cycles.
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if r_clkmod_cnt = 1 or r_clkmod_cnt = 4 or r_clkmod_cnt = 5 or
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r_clkmod_cnt = 7 or r_clkmod_cnt = 12 then
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r_clkmod_tmp <= '1';
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else
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r_clkmod_tmp <= '0';
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end if;
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r_clkmod_cnt <= r_clkmod_cnt + 1;
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if rst = '1' then
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r_clkmod_cnt <= (others => '0');
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r_clkmod_tmp <= '0';
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r_clk_en <= '1';
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end if;
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end if;
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end process;
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-- Synchronous process.
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-- Byte-level serial protocol.
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process (clk) is
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begin
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if rising_edge(clk) then
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r_ser_tx_strobe <= '0';
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r_tst_start <= '0';
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if r_ctl_state = "0000" and
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r_ser_rx_strobe = '1' and r_ser_rx_byte = x"41" then
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r_ctl_state <= "0001";
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end if;
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if r_ctl_state = "0001" and r_ser_rx_strobe = '1' then
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if r_ser_rx_byte = x"42" then
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r_ctl_state <= "0010";
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elsif r_ser_rx_byte = x"43" then
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r_ctl_state <= "0000";
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r_clkmod <= '1';
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elsif r_ser_rx_byte = x"44" then
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r_ctl_state <= "0000";
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r_clkmod <= '0';
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else
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r_ctl_state <= "0000";
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end if;
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end if;
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if r_ctl_state = "0010" and r_ser_rx_strobe = '1' then
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r_ctl_state <= "0011";
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r_tst_in_phase <= unsigned(r_ser_rx_byte) & r_tst_in_phase(31 downto 8);
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end if;
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if r_ctl_state = "0011" and r_ser_rx_strobe = '1' then
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r_ctl_state <= "0100";
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r_tst_in_phase <= unsigned(r_ser_rx_byte) & r_tst_in_phase(31 downto 8);
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end if;
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if r_ctl_state = "0100" and r_ser_rx_strobe = '1' then
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r_ctl_state <= "0101";
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r_tst_in_phase <= unsigned(r_ser_rx_byte) & r_tst_in_phase(31 downto 8);
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end if;
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if r_ctl_state = "0101" and r_ser_rx_strobe = '1' then
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r_ctl_state <= "0110";
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r_tst_in_phase <= unsigned(r_ser_rx_byte) & r_tst_in_phase(31 downto 8);
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r_tst_start <= '1';
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end if;
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if r_ctl_state = "0110" and r_tst_start = '0' and r_tst_busy = '0' then
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r_ctl_state <= "0111";
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end if;
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if r_ctl_state = "0111" and r_ser_tx_busy = '0' then
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r_ctl_state <= "1000";
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r_ser_tx_byte <= std_logic_vector(r_tst_out_sin(7 downto 0))
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r_ser_tx_strobe <= '1';
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end if;
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if r_ctl_state = "1000" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
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r_ctl_state <= "1001";
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r_ser_tx_byte <= std_logic_vector(r_tst_out_sin(15 downto 8))
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r_ser_tx_strobe <= '1';
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end if;
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if r_ctl_state = "1001" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
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r_ctl_state <= "1010";
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r_ser_tx_byte <= std_logic_vector(r_tst_out_sin(23 downto 15))
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r_ser_tx_strobe <= '1';
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end if;
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if r_ctl_state = "1010" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
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r_ctl_state <= "1011";
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r_ser_tx_byte <= std_logic_vector(r_tst_out_sin(31 downto 24))
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r_ser_tx_strobe <= '1';
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end if;
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if r_ctl_state = "1011" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
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r_ctl_state <= "1100";
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r_ser_tx_byte <= std_logic_vector(r_tst_out_cos(7 downto 0))
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r_ser_tx_strobe <= '1';
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end if;
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if r_ctl_state = "1100" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
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r_ctl_state <= "1101";
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r_ser_tx_byte <= std_logic_vector(r_tst_out_cos(15 downto 8))
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r_ser_tx_strobe <= '1';
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end if;
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if r_ctl_state = "1101" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
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r_ctl_state <= "1110";
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r_ser_tx_byte <= std_logic_vector(r_tst_out_cos(23 downto 15))
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r_ser_tx_strobe <= '1';
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end if;
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if r_ctl_state = "1110" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
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r_ctl_state <= "0000";
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r_ser_tx_byte <= std_logic_vector(r_tst_out_cos(31 downto 24))
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r_ser_tx_strobe <= '1';
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end if;
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-- Synchronous reset.
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if rst = '1' then
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r_ctl_state <= "0000";
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r_clkmod <= '0';
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end if;
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end if;
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end process;
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-- Synchronous process.
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-- Serial port RX machine.
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process (clk) is
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begin
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if rising_edge(clk) then
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-- Default.
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r_ser_rx_strobe <= '0';
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-- Deglitch filter.
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r_ser_rx_glitch <= r_ser_rx_glitch(6 downto 0) & ser_rx;
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if r_ser_rx_glitch(7 downto 1) = "0000000" then
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r_ser_rxbit <= '0';
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elsif r_ser_rx_glitch(7 downto 1) = "1111111" then
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r_ser_rxbit <= '1';
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end if;
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-- Bit timer.
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r_ser_rx_timer <= r_ser_rx_timer - 1;
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if r_ser_rx_timer = 0 then
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r_ser_rx_timeout <= '1';
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else
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r_ser_rx_timeout <= '0';
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end if;
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-- RX state machine.
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if r_ser_rx_state = "00" then
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-- Wait for idle level.
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if r_ser_rx_bit = '1' then
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r_ser_rx_state <= "01";
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end if;
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elsif r_ser_rx_state = "01" then
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-- Wait for start of byte.
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r_ser_rx_shift(7 downto 0) <= (others => '0');
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r_ser_rx_shift(8) <= '1';
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r_ser_rx_timer <= to_unsigned(serial_bitrate_divider / 2 - 2, 13);
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r_ser_rx_timeout <= '0';
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if r_ser_rx_bit = '0' then
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r_ser_rx_state <= "10";
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end if;
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elsif r_ser_rx_state = "10" then
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-- Wait for data bit.
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if r_ser_rx_timeout = '1' then
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r_ser_rx_shift <= r_ser_rx_bit & r_ser_rx_shift(8 downto 1);
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if r_ser_rx_shift(0) = '1' then
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-- Reached end of byte.
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if r_ser_rx_bit = '1' then
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-- Got valid stop bit.
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r_ser_rx_strobe <= '1';
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r_ser_rx_state <= "01";
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else
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-- Got invalid stop bit.
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r_ser_rx_state <= "00";
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end if;
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r_ser_rx_state <= "11";
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end if;
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r_ser_rx_timer <= to_unsigned(serial_bitrate_divider - 2);
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end if;
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else
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-- Invalid state.
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r_ser_rx_state <= "00";
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end if;
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-- Synchronous reset.
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if rst = '1' then
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r_ser_rx_state <= "00";
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r_ser_rx_strobe <= '0';
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end if;
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end if;
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end process;
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-- Synchronous process.
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-- Serial port TX machine.
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process (clk) is
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begin
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if rising_edge(clk) then
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-- Drive output register.
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ser_tx <= r_ser_tx_bit;
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-- Bit timer.
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r_ser_tx_timer <= r_ser_tx_timer - 1;
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if r_ser_tx_timer = 0 then
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r_ser_tx_timeout <= '1';
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else
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r_ser_tx_timeout <= '0';
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end if;
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if r_ser_tx_busy = '0' then
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-- Wait for start of byte.
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r_ser_tx_timer <= to_unsigned(serial_bitrate_divider - 2, 13);
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r_ser_tx_timeout <= '0';
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r_ser_tx_shift <= r_ser_tx_byte;
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r_ser_tx_bitcnt <= to_unsigned(9, 4);
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if r_ser_tx_strobe = '1' then
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-- Start new byte.
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r_ser_tx_bit <= '0';
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r_ser_tx_busy <= '1';
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end if;
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elsif r_ser_tx_busy = '1' and r_ser_tx_timout = '1' then
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-- Send next bit.
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r_ser_tx_bit <= r_ser_tx_shift(0);
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r_ser_tx_shift <= "1" & r_ser_tx_shift(7 downto 1);
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r_ser_tx_bitcnt <= r_ser_tx_bitcnt - 1;
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r_ser_tx_timer <= to_unsigned(serial_bitrate_divider - 2, 13);
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if r_ser_tx_bitcnt = 0 then
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-- Just completed stop bit.
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r_ser_tx_busy <= '0';
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end if;
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end if;
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-- Synchronous reset.
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if rst = '1' then
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r_ser_tx_busy <= '0';
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r_ser_tx_bit <= '1';
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end if;
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end if;
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end process;
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end architecture;
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