vhdl-sincos-gen/synth/digilent_atlys
Joris van Rantwijk e402b88b3d Minor change to atlys toplevel.
* Rename .vhd -> .vhdl
* Reset phase of audio tone.
2016-04-22 21:06:40 +02:00
..
ac97out.vhdl Integrate AC97 output in Atlys top-level. 2016-04-22 19:34:39 +02:00
atlys.ucf Add top-level test design for Digilent Atlys board. 2016-04-22 09:42:48 +02:00
test_sincos.gise Minor change to atlys toplevel. 2016-04-22 21:06:40 +02:00
test_sincos.xise Minor change to atlys toplevel. 2016-04-22 21:06:40 +02:00
top_test_sincos.vhdl Minor change to atlys toplevel. 2016-04-22 21:06:40 +02:00