46 lines
1.2 KiB
VHDL
46 lines
1.2 KiB
VHDL
--
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-- Top-level design for synthesis dry-run of the sine / cosine function core.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity top_d18_p20 is
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port (
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clk: in std_logic;
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clk_en: in std_logic;
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in_phase: in std_logic_vector(19 downto 0);
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out_sin: out std_logic_vector(17 downto 0);
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out_cos: out std_logic_vector(17 downto 0) );
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end entity;
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architecture rtl of top_d18_p20 is
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signal r_in_phase: unsigned(19 downto 0);
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signal s_out_sin: signed(17 downto 0);
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signal s_out_cos: signed(17 downto 0);
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begin
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-- Instantiate core.
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gen0: entity work.sincos_gen_d18_p20
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port map (
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clk => clk,
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clk_en => clk_en,
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in_phase => r_in_phase,
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out_sin => s_out_sin,
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out_cos => s_out_cos );
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-- Input/output flip-flops.
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process (clk) is
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begin
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if rising_edge(clk) then
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r_in_phase <= unsigned(in_phase);
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out_sin <= std_logic_vector(s_out_sin);
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out_cos <= std_logic_vector(s_out_cos);
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end if;
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end process;
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end architecture;
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