89 lines
2.2 KiB
VHDL
89 lines
2.2 KiB
VHDL
--
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-- Top-level simulation test bench to probe sincos_gen_d24_p26
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-- at a couple of test inputs.
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--
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-- Joris van Rantwijk
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity sim_sincos_d24_p26_probe is
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end entity;
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architecture arch of sim_sincos_d24_p26_probe is
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type input_list_type is array(natural range <>) of integer;
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constant input_list: input_list_type(0 to 9) := (
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0, -- 0 rad
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12345, -- 0.00115582 rad
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1234567, -- 0.11558850 rad
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8388608, -- 45 degrees
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10680707, -- 0.99999996 rad
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16777216, -- 90 degrees
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20304050, -- 1.90100236 rad
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34567890, -- 3.23647944 rad
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42722830, -- 4.00000003 rad
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65244729 ); -- 350.000001 degrees
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signal clk_enable: boolean := false;
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signal clk: std_logic;
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signal clk_en: std_logic;
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signal in_phase: unsigned(25 downto 0);
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signal out_sin: signed(23 downto 0);
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signal out_cos: signed(23 downto 0);
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begin
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clk <= (not clk) after 2 ns when clk_enable else '0';
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gen0: entity work.sincos_gen_d24_p26
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port map (
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clk => clk,
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clk_en => clk_en,
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in_phase => in_phase,
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out_sin => out_sin,
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out_cos => out_cos );
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process is
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begin
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clk_enable <= true;
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clk_en <= '0';
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in_phase <= (others => '0');
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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clk_en <= '1';
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-- Probe at a few different inputs.
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for i in 0 to input_list'high+9 loop
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if i <= input_list'high then
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in_phase <= to_unsigned(input_list(i), 26);
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end if;
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if i >= 9 then
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report " phase=" & integer'image(input_list(i-9)) &
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" sin=" & integer'image(to_integer(out_sin)) &
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" cos=" & integer'image(to_integer(out_cos));
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end if;
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wait until falling_edge(clk);
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end loop;
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clk_en <= '0';
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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clk_enable <= false;
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wait;
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end process;
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end arch;
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