65 lines
1.5 KiB
VHDL
65 lines
1.5 KiB
VHDL
--
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-- Wrapper for sine / cosine function core
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--
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-- Copyright 2016 Joris van Rantwijk
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--
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-- This design is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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--
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-- Phase input:
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-- unsigned 20 bits (2**20 steps for a full circle)
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--
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-- Sin/cos output:
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-- signed 18 bits (nominal amplitude = 2**17-1)
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--
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-- Latency:
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-- 6 clock cycles
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity sincos_gen_d18_p20 is
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port (
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-- System clock, active on rising edge.
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clk: in std_logic;
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-- Clock enable.
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clk_en: in std_logic;
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-- Phase input.
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in_phase: in unsigned(19 downto 0);
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-- Sine output.
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-- (6 clock cycles latency after in_phase).
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out_sin: out signed(17 downto 0);
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-- Cosine output.
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-- (6 clock cycles latency after in_phase).
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out_cos: out signed(17 downto 0) );
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end entity;
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architecture rtl of sincos_gen_d18_p20 is
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begin
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gen0: entity work.sincos_gen
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generic map (
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data_bits => 18,
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phase_bits => 20,
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phase_extrabits => 2,
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table_addrbits => 10,
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taylor_order => 1 )
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port map (
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clk => clk,
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clk_en => clk_en,
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in_phase => in_phase,
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out_sin => out_sin,
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out_cos => out_cos );
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end architecture;
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