vhdl-sincos-gen/rtl
Joris van Rantwijk 385c9f5ed2 * Finally found a way to describe the lookup table such that both
ISE and Vivado infer a dual-port block RAM.
2016-04-19 23:36:10 +02:00
..
sincos_gen.vhdl * Finally found a way to describe the lookup table such that both 2016-04-19 23:36:10 +02:00
sincos_gen_d18_p20.vhdl * Reorganize comments at top of wrappers for sin/cos generator. 2016-04-16 22:16:20 +02:00
sincos_gen_d24_p26.vhdl * Reorganize comments at top of wrappers for sin/cos generator. 2016-04-16 22:16:20 +02:00
test_sincos_serial.vhdl * Implement serial port interface in test design. 2016-04-18 21:14:31 +02:00