236 lines
7.1 KiB
VHDL
236 lines
7.1 KiB
VHDL
--
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-- Simple core for AC97 audio output.
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--
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-- Sets output volume to -12 dB,
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-- then plays stereo PCM data at 48 kHz sample rate.
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-- Only tested with LM4550 on Digilent Atlys board.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ac97out is
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port (
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-- AC97 bit clock.
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bitclk: in std_logic;
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-- Asynchronous reset, active low.
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resetn: in std_logic;
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-- Input samples for left and right channel.
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data_left: in signed(19 downto 0);
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data_right: in signed(19 downto 0);
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-- Data handshake.
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data_valid: in std_logic;
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data_ready: out std_logic;
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-- AC97 interface signals.
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ac97_sdi: in std_logic;
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ac97_sdo: out std_logic;
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ac97_sync: out std_logic );
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end entity;
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architecture rtl of ac97out is
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-- Initialization sequence.
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type init_table_type is array(0 to 7) of std_logic_vector(23 downto 0);
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constant init_table: init_table_type := (
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-- write 0x0000 to register 0x00: soft reset
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x"000000",
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-- write 0x0000 to register 0x02: set master volume to -12 dB
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x"020808",
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-- write 0x0000 to register 0x04: set headphone volume to -12 dB
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x"040808",
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-- write 0x0000 to register 0x06: set mono_out volume to -12 dB
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x"060008",
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-- write 0x0808 to register 0x18: set PCM out volume to 0 dB
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x"180808",
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-- dummy read from register 0x00
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x"800000",
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x"800000",
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x"800000" );
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-- Output registers.
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signal r_ready: std_logic;
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signal r_sdo: std_logic;
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signal r_sync: std_logic;
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-- Reset synchronization.
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signal r_rstsync: std_logic_vector(7 downto 0);
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-- Bit counter.
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signal r_bitcnt: unsigned(7 downto 0);
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signal r_lastbit: std_logic;
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signal r_endsync: std_logic;
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-- Initialization state machine.
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signal r_initwait: unsigned(5 downto 0);
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signal r_initbusy: std_logic;
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signal r_initdone: std_logic;
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signal r_initstep: unsigned(2 downto 0);
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signal r_initword: std_logic_vector(23 downto 0);
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-- Data for next frame.
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signal r_datavalid: std_logic;
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signal r_dataleft: std_logic_vector(19 downto 0);
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signal r_dataright: std_logic_vector(19 downto 0);
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-- Frame data shift register (tag + slots 1 .. 4)
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signal r_sdoshift: std_logic_vector(95 downto 0);
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-- AC97 bit input register
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signal r_sdi: std_logic;
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begin
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-- Drive outputs.
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data_ready <= r_ready;
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ac97_sdo <= r_sdo;
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ac97_sync <= r_sync;
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-- Synchronous process.
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-- Sample AC97_SDI on falling edge of BITCLK.
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process (bitclk) is
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begin
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if falling_edge(bitclk) then
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r_sdi <= ac97_sdi;
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end if;
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end process;
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-- Synchronous process.
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process (bitclk, resetn) is
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begin
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if resetn = '0' then
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-- Asynchronous reset.
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r_rstsync <= (others => '0');
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r_ready <= '0';
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-- Outputs to codec must be low during reset.
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r_sdo <= '0';
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r_sync <= '0';
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elsif rising_edge(bitclk) then
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-- Drive SYNC high for 16 cycles at start of frame.
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if r_lastbit = '1' then
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r_sync <= '1';
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elsif r_endsync = '1' then
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r_sync <= '0';
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end if;
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-- Push next data bit to output.
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r_sdo <= r_sdoshift(r_sdoshift'high);
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r_sdoshift <= r_sdoshift(r_sdoshift'high-1 downto 0) & "0";
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-- Fetch data from init table.
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r_initword <= init_table(to_integer(r_initstep));
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-- Prepare next frame.
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if r_lastbit = '1' then
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-- sdoshift(95:80) = TAG
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-- bit 15 = master valid bit
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-- bit 14 = slot 1 valid
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-- bit 13 = slot 2 valid
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-- bit 12 = slot 3 valid
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-- bit 11 = slot 4 valid
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-- Always set frame valid.
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r_sdoshift(95) <= '1';
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-- Set slots 1 and 2 valid if we are initializing.
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r_sdoshift(94) <= r_initbusy;
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r_sdoshift(93) <= r_initbusy;
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-- Set slots 3 and 4 valid if we have valid data.
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r_sdoshift(92) <= r_datavalid;
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r_sdoshift(91) <= r_datavalid;
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-- Remaining tag bits always zero.
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r_sdoshift(90 downto 80) <= (others => '0');
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-- Slot 1: Register read/write command.
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-- bit 19 = read (1) or write (0)
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-- bit 18:12 = address
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r_sdoshift(79 downto 72) <= r_initword(23 downto 16);
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r_sdoshift(71 downto 60) <= (others => '0');
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-- Slot 2: Register write data.
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-- bit 19:4 = data
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r_sdoshift(59 downto 44) <= r_initword(15 downto 0);
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r_sdoshift(43 downto 40) <= (others => '0');
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-- Update init pointer.
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if r_initbusy = '1' then
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r_initstep <= r_initstep + 1;
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end if;
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if r_initstep = 7 then
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r_initbusy <= '0';
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r_initdone <= '1';
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end if;
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-- Update init delay counter (wait for 1.3 ms after reset).
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r_initwait <= r_initwait - 1;
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if r_initwait = 0 then
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r_initstep <= (others => '0');
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r_initbusy <= not r_initdone;
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end if;
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-- Slots 3 and 4: left and right sample value.
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r_sdoshift(39 downto 20) <= r_dataleft;
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r_sdoshift(19 downto 0) <= r_dataright;
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-- Consume sample values.
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r_datavalid <= '0';
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r_ready <= '1';
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end if;
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-- Update bit counter.
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r_bitcnt <= r_bitcnt - 1;
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if r_bitcnt = 1 then
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r_lastbit <= '1';
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else
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r_lastbit <= '0';
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end if;
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if r_bitcnt = 241 then
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r_endsync <= '1';
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else
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r_endsync <= '0';
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end if;
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-- Capture input data.
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if r_ready = '1' and data_valid = '1' then
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r_ready <= '0';
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r_datavalid <= '1';
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r_dataleft <= std_logic_vector(data_left);
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r_dataright <= std_logic_vector(data_right);
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end if;
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-- Release synchronous reset.
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r_rstsync <= "1" & r_rstsync(7 downto 1);
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-- Synchronous reset.
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if r_rstsync(0) = '0' then
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r_ready <= '0';
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r_sdo <= '0';
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r_sync <= '0';
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r_initbusy <= '0';
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r_initdone <= '0';
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r_initwait <= (others => '1');
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r_initstep <= (others => '0');
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r_bitcnt <= (others => '0');
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r_datavalid <= '0';
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end if;
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end if;
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end process;
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end architecture;
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