79 lines
1.8 KiB
VHDL
79 lines
1.8 KiB
VHDL
--
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-- Top-level simulation test bench to test sincos_gen_d24_p26
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-- for all possible inputs.
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--
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-- Joris van Rantwijk
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--
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library std;
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use std.textio.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity sim_sincos_d24_p26_full is
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end entity;
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architecture arch of sim_sincos_d24_p26_full is
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constant latency: integer := 9;
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constant phaserange: integer := 2**26;
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signal clk_enable: boolean := false;
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signal clk: std_logic;
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signal clk_en: std_logic;
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signal in_phase: unsigned(25 downto 0);
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signal out_sin: signed(23 downto 0);
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signal out_cos: signed(23 downto 0);
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begin
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clk <= (not clk) after 2 ns when clk_enable else '0';
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gen0: entity work.sincos_gen_d24_p26
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port map (
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clk => clk,
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clk_en => clk_en,
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in_phase => in_phase,
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out_sin => out_sin,
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out_cos => out_cos );
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process is
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constant strspace: string := " ";
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file outf: text is out "sim_sincos_d24_p26_full.dat";
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variable lin: line;
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begin
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clk_enable <= true;
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clk_en <= '0';
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in_phase <= (others => '0');
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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clk_en <= '1';
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-- Test at all possible inputs.
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for p in 0 to phaserange+latency loop
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in_phase <= to_unsigned(p, 26);
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if p >= latency and p < phaserange+latency then
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write(lin, to_integer(out_sin));
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write(lin, strspace);
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write(lin, to_integer(out_cos));
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writeline(outf, lin);
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end if;
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wait until falling_edge(clk);
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end loop;
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clk_enable <= false;
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wait;
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end process;
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end arch;
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