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Author SHA1 Message Date
Joris van Rantwijk 398dca67b6 Fix bugs in AC97 output for Atlys board. 
* Fix bugs in AC97 synchronization.
* Fix bugs in AC97 reset.
* Reduce audio volume to -12 dB.
* Set correct voltage for reset button on Atlys board.
 2016-04-23 11:37:42 +02:00
Joris van Rantwijk 8bd2d389ef Add Python program to test core via serial port. 2016-04-23 00:27:34 +02:00
Joris van Rantwijk e402b88b3d Minor change to atlys toplevel. 
* Rename .vhd -> .vhdl
* Reset phase of audio tone.
 2016-04-22 21:06:40 +02:00
Joris van Rantwijk 01c0832324 Integrate AC97 output in Atlys top-level. 2016-04-22 19:34:39 +02:00
Joris van Rantwijk 47e53fff56 Add AC97 output driver. 2016-04-22 17:20:13 +02:00
Joris van Rantwijk 9c73463282 Add top-level test design for Digilent Atlys board. 2016-04-22 09:42:48 +02:00
Joris van Rantwijk 331211f34b Fix bugs in test_sincos_serial.vhdl. 
* Allow choice of core at run-time instead of synthesis-time.
* Fix mistake in serial port RX machine.
 2016-04-21 22:20:32 +02:00
Joris van Rantwijk 84c92fea95 Fix analysis errors in test_sincos_serial.vhdl. 2016-04-21 20:36:11 +02:00
Joris van Rantwijk b21a696b71 Minor textual improvements in README. 2016-04-21 20:30:53 +02:00
Joris van Rantwijk ff860d4ae3 Update README after adding extra phase bit. 
* Update accuracy figures based on simulation with extra phase bit.
* Update FPGA resource information based on synthesis run with extra phase bit.
 2016-04-21 20:26:03 +02:00
8 changed files with 1295 additions and 107 deletions
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65
README.txt
View File

@ -1,8 +1,8 @@
Sine / cosine generator in VHDL
=================================
Sine / cosine function core in VHDL
====================================
This package contains a sine / cosine generator in synthesizable VHDL code.
This package contains a sine / cosine function core in synthesizable VHDL code.
The core takes a phase value as input and produces the corresponding sine
and cosine as signed integer outputs. The core is fully pipelined, accepting
@ -33,8 +33,8 @@ to compute the sine and cosine of an arbitrary point in the first quadrant:
in a ROM block with two read ports.
2) Compute the phase mismatch between the table point and actual
phase input in radians. This requires multiplication by Pi,
which is implemented through repeated shifting and adding.
phase input in radians. This requires multiplication by Pi/2,
which is implemented through shifting and adding.
3) Use the Taylor series to obtain a more accurate approximation
of the answer. Depending on the required accuracy, either 1st order
@ -106,24 +106,22 @@ Accuracy of the sine/cosine output from the cores has been determined from
a simulation of the VHDL code on all possible phase input values.
----
Core variant: sincos_gen_d18_p20 sincos_gen_d24_p26
Phase input width: 20 bits 26 bits
Sin/cos output width: 18 bits 24 bits
Core variant sincos_gen_d18_p20 sincos_gen_d24_p26
Phase input width 20 bits 26 bits
Sin/cos output width 18 bits 24 bits
Amplitude: 131071.008128 lsb 8388606.997508 lsb
Offset: 0.000000 lsb 0.000000 lsb
Phase mismatch: 1.30e-7 rad 1.94e-9 rad
Amplitude 131071.008033 lsb 8388606.997478 lsb
Offset 0.000000 lsb 0.000000 lsb
Phase mismatch 1.30e-7 rad 1.99e-9 rad
Peak absolute error 0.966104 lsb 1.029916 lsb
Root-mean-square error 0.330982 lsb rms 0.332547 lsb rms
SINAD 108.94 dB 145.03 dB
Effective nr of bits 17.80 bits 23.80 bits
Spurious-free dynamic range 129.81 dB 166.18 dB
cos(x) == sin(x+pi/2) exact match exact match
sin(x) == - sin(x+pi) exact match exact match
Peak absolute error: 0.864721 lsb 0.917662 lsb
Root-mean-square error: 0.325144 lsb rms 0.326538 lsb rms
SINAD: 109.09 dB 145.18 dB
Effective nr of bits: 17.83 bits 23.82 bits
Spurious-free dynamic range: 135.19 dB 171.50 dB
cos(x) == sin(x+pi/2) : exact match exact match
sin(x) == - sin(x+pi) : exact match exact match
----
@ -131,22 +129,21 @@ sin(x) == - sin(x+pi) exact match exact match
--------------
----
FPGA type: Xilinx Spartan-6 LX45-3 Xilinx Virtex-7 485T-1
Synthesizer: Xilinx ISE 14.7 Xilinx Vivado 2014.4.1
FPGA type Xilinx Spartan-6 LX45-3 Xilinx Virtex-7 485T-1
Synthesizer Xilinx ISE 14.7 Xilinx Vivado 2014.4.1
Core variant: d18_p20 d24_p26 d18_p20 d24_p26
Core variant d18_p20 d24_p26 d18_p20 d24_p26
Flip-flops 134 250 151 291
LUTs 118 204 115 181
RAMB18 0 0 1 0
RAMB36 0 0 0 1
DSP48E1 0 0 2 4
RAMB16BWER 1 1
RAMB8BWER 0 1
DSP48A1 2 4
Clock freq 230 MHz 230 MHz 400 MHz 400 MHz
Flip-flops: 136 253 153 295
LUTs: 124 213 114 182
RAMB18: 0 0 1 0
RAMB36: 0 0 0 1
DSP48E1: 0 0 2 4
RAMB16BWER: 1 1
RAMB8BWER: 0 1
DSP48A1: 2 4
Clock freq: 230 MHz 230 MHz 400 MHz 400 MHz
----
--

187
rtl/test_sincos_serial.vhdl
View File

@ -7,6 +7,22 @@
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
--
--
-- Test driver for sine / cosine core, communicates via serial port.
--
-- Send 6 bytes { 0x41 0x42 phase(7:0) phase(15:8) phase(23:16) phase(31:24) }
-- to calculate sine and cosine of phase on the 18-bit / 20-bit core.
--
-- Send 6 bytes { 0x41 0x43 phase(7:0) phase(15:8) phase(23:16) phase(31:24) }
-- to calculate sine and cosine of phase on the 24-bit / 26-bit core.
--
-- In both cases, test driver replies with 8 bytes
-- { sin(7:0) sin(15:8) sin(23:16) sin(31:24)
-- cos(7:0) cos(15:8) cos(23:16) cos(31:24 }
--
-- Send 2 bytes { 0x41 0x44 } to start clock-enable modulation.
-- Send 3 bytes { 0x41 0x45 } to stop clock-enable modulation.
--
library ieee;
use ieee.std_logic_1164.all;
@ -17,12 +33,7 @@ entity test_sincos_serial is
generic (
-- Clock frequency divider from system clock to serial bitrate.
-- bitrate = system_clock_frequency / serial_bitrate_divider
serial_bitrate_divider: integer range 10 to 8192;
-- Select core.
-- 1 = 18-bit sin/cos generator;
-- 2 = 24-bit sin/cos generator.
core_select: integer range 1 to 2 );
serial_bitrate_divider: integer range 10 to 8192 );
port (
-- System clock, active on rising edge.
@ -35,27 +46,33 @@ entity test_sincos_serial is
ser_rx: in std_logic;
-- Serial TX output.
ser_tx: out std_logic );
ser_tx: out std_logic;
-- Status signals.
stat_ready: out std_logic;
stat_calc: out std_logic;
stat_clkmod: out std_logic;
stat_txser: out std_logic );
end entity;
architecture rtl of test_sincos_serial is
constant latency: integer := 3 + 3 * core_select;
constant core1_latency: integer := 6;
constant core2_latency: integer := 9;
signal r_clk_en: std_logic;
signal r_in_phase: unsigned(31 downto 0);
signal s_out_sin: signed(31 downto 0);
signal s_out_cos: signed(31 downto 0);
signal s_gen1_out_sin: signed(17 downto 0);
signal s_gen1_out_cos: signed(17 downto 0);
signal s_gen2_out_sin: signed(23 downto 0);
signal s_gen2_out_cos: signed(23 downto 0);
signal r_tst_start: std_logic;
signal r_tst_in_phase: unsigned(31 downto 0);
signal r_tst_out_sin: unsigned(31 downto 0);
signal r_tst_out_cos: unsigned(31 downto 0);
signal r_tst_coresel: std_logic;
signal r_tst_in_phase: std_logic_vector(31 downto 0);
signal r_tst_out_sin: std_logic_vector(31 downto 0);
signal r_tst_out_cos: std_logic_vector(31 downto 0);
signal r_tst_busy: std_logic;
signal r_tst_cyclecnt: unsigned(3 downto 0);
@ -71,7 +88,7 @@ architecture rtl of test_sincos_serial is
signal r_ser_rx_bit: std_logic;
signal r_ser_rx_timer: unsigned(12 downto 0);
signal r_ser_rx_timeout: std_logic;
signal r_ser_rx_state; std_logic_vector(1 downto 0);
signal r_ser_rx_state: std_logic_vector(1 downto 0);
signal r_ser_rx_shift: std_logic_vector(8 downto 0);
signal r_ser_tx_strobe: std_logic;
@ -86,36 +103,22 @@ architecture rtl of test_sincos_serial is
begin
-- Instantiate 18-bit sin/cos core.
gen1: if core_select = 1 generate
gen1x: entity work.sincos_gen_d18_p20
port map (
clk => clk,
clk_en => r_clk_en,
in_phase => r_in_phase(19 downto 0),
out_sin => s_gen1_out_sin,
out_cos => s_gen1_out_cos );
s_out_sin <= resize(s_gen1_out_sin, 32);
s_out_cos <= resize(s_gen1_out_cos, 32);
end generate;
gen1: entity work.sincos_gen_d18_p20
port map (
clk => clk,
clk_en => r_clk_en,
in_phase => r_in_phase(19 downto 0),
out_sin => s_gen1_out_sin,
out_cos => s_gen1_out_cos );
-- Instantiate 24-bit sin/cos core.
gen2: if core_select = 2 generate
gen2x: entity work.sincos_gen_d24_p26
port map (
clk => clk,
clk_en => r_clk_en,
in_phase => r_in_phase(25 downto 0),
out_sin => s_gen2_out_sin,
out_cos => s_gen2_out_cos );
s_out_sin <= resize(s_gen2_out_sin, 32);
s_out_cos <= resize(s_gen2_out_cos, 32);
end generate;
gen2: entity work.sincos_gen_d24_p26
port map (
clk => clk,
clk_en => r_clk_en,
in_phase => r_in_phase(25 downto 0),
out_sin => s_gen2_out_sin,
out_cos => s_gen2_out_cos );
-- Synchronous process.
-- State machine for interface to design under test.
@ -128,15 +131,23 @@ begin
r_in_phase <= (others => '0');
end if;
if r_tst_busy = '1' and r_tst_cyclecnt = latency then
if r_tst_busy = '1' and r_tst_coresel = '0' and
r_tst_cyclecnt = core1_latency then
r_tst_busy <= '0';
r_tst_out_sin <= s_out_sin;
r_tst_out_cos <= s_out_cos;
r_tst_out_sin <= std_logic_vector(resize(s_gen1_out_sin, 32));
r_tst_out_cos <= std_logic_vector(resize(s_gen1_out_cos, 32));
end if;
if r_tst_busy = '1' and r_tst_coresel = '1' and
r_tst_cyclecnt = core2_latency then
r_tst_busy <= '0';
r_tst_out_sin <= std_logic_vector(resize(s_gen2_out_sin, 32));
r_tst_out_cos <= std_logic_vector(resize(s_gen2_out_cos, 32));
end if;
if r_tst_start = '1' and r_tst_busy = '0' then
r_tst_busy <= '1';
r_in_phase <= r_tst_in_phase;
r_in_phase <= unsigned(r_tst_in_phase);
r_tst_cyclecnt <= (others => '0');
end if;
@ -197,10 +208,14 @@ begin
if r_ctl_state = "0001" and r_ser_rx_strobe = '1' then
if r_ser_rx_byte = x"42" then
r_ctl_state <= "0010";
r_tst_coresel <= '0';
elsif r_ser_rx_byte = x"43" then
r_ctl_state <= "0010";
r_tst_coresel <= '1';
elsif r_ser_rx_byte = x"44" then
r_ctl_state <= "0000";
r_clkmod <= '1';
elsif r_ser_rx_byte = x"44" then
elsif r_ser_rx_byte = x"45" then
r_ctl_state <= "0000";
r_clkmod <= '0';
else
@ -210,22 +225,22 @@ begin
if r_ctl_state = "0010" and r_ser_rx_strobe = '1' then
r_ctl_state <= "0011";
r_tst_in_phase <= unsigned(r_ser_rx_byte) & r_tst_in_phase(31 downto 8);
r_tst_in_phase <= r_ser_rx_byte & r_tst_in_phase(31 downto 8);
end if;
if r_ctl_state = "0011" and r_ser_rx_strobe = '1' then
r_ctl_state <= "0100";
r_tst_in_phase <= unsigned(r_ser_rx_byte) & r_tst_in_phase(31 downto 8);
r_tst_in_phase <= r_ser_rx_byte & r_tst_in_phase(31 downto 8);
end if;
if r_ctl_state = "0100" and r_ser_rx_strobe = '1' then
r_ctl_state <= "0101";
r_tst_in_phase <= unsigned(r_ser_rx_byte) & r_tst_in_phase(31 downto 8);
r_tst_in_phase <= r_ser_rx_byte & r_tst_in_phase(31 downto 8);
end if;
if r_ctl_state = "0101" and r_ser_rx_strobe = '1' then
r_ctl_state <= "0110";
r_tst_in_phase <= unsigned(r_ser_rx_byte) & r_tst_in_phase(31 downto 8);
r_tst_in_phase <= r_ser_rx_byte & r_tst_in_phase(31 downto 8);
r_tst_start <= '1';
end if;
@ -235,49 +250,49 @@ begin
if r_ctl_state = "0111" and r_ser_tx_busy = '0' then
r_ctl_state <= "1000";
r_ser_tx_byte <= std_logic_vector(r_tst_out_sin(7 downto 0))
r_ser_tx_byte <= r_tst_out_sin(7 downto 0);
r_ser_tx_strobe <= '1';
end if;
if r_ctl_state = "1000" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
r_ctl_state <= "1001";
r_ser_tx_byte <= std_logic_vector(r_tst_out_sin(15 downto 8))
r_ser_tx_byte <= r_tst_out_sin(15 downto 8);
r_ser_tx_strobe <= '1';
end if;
if r_ctl_state = "1001" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
r_ctl_state <= "1010";
r_ser_tx_byte <= std_logic_vector(r_tst_out_sin(23 downto 15))
r_ser_tx_byte <= r_tst_out_sin(23 downto 16);
r_ser_tx_strobe <= '1';
end if;
if r_ctl_state = "1010" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
r_ctl_state <= "1011";
r_ser_tx_byte <= std_logic_vector(r_tst_out_sin(31 downto 24))
r_ser_tx_byte <= r_tst_out_sin(31 downto 24);
r_ser_tx_strobe <= '1';
end if;
if r_ctl_state = "1011" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
r_ctl_state <= "1100";
r_ser_tx_byte <= std_logic_vector(r_tst_out_cos(7 downto 0))
r_ser_tx_byte <= r_tst_out_cos(7 downto 0);
r_ser_tx_strobe <= '1';
end if;
if r_ctl_state = "1100" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
r_ctl_state <= "1101";
r_ser_tx_byte <= std_logic_vector(r_tst_out_cos(15 downto 8))
r_ser_tx_byte <= r_tst_out_cos(15 downto 8);
r_ser_tx_strobe <= '1';
end if;
if r_ctl_state = "1101" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
r_ctl_state <= "1110";
r_ser_tx_byte <= std_logic_vector(r_tst_out_cos(23 downto 15))
r_ser_tx_byte <= r_tst_out_cos(23 downto 16);
r_ser_tx_strobe <= '1';
end if;
if r_ctl_state = "1110" and r_ser_tx_strobe = '0' and r_ser_tx_busy = '0' then
r_ctl_state <= "0000";
r_ser_tx_byte <= std_logic_vector(r_tst_out_cos(31 downto 24))
r_ser_tx_byte <= r_tst_out_cos(31 downto 24);
r_ser_tx_strobe <= '1';
end if;
@ -290,6 +305,25 @@ begin
end if;
end process;
-- Synchronous process.
-- Drive status output signals.
process (clk) is
begin
if rising_edge(clk) then
if r_ctl_state = "0000" then
stat_ready <= '1';
else
stat_ready <= '0';
end if;
stat_calc <= r_tst_busy;
stat_clkmod <= r_clkmod;
stat_txser <= r_ser_tx_busy;
end if;
end process;
-- Synchronous process.
-- Serial port RX machine.
process (clk) is
@ -302,9 +336,9 @@ begin
-- Deglitch filter.
r_ser_rx_glitch <= r_ser_rx_glitch(6 downto 0) & ser_rx;
if r_ser_rx_glitch(7 downto 1) = "0000000" then
r_ser_rxbit <= '0';
r_ser_rx_bit <= '0';
elsif r_ser_rx_glitch(7 downto 1) = "1111111" then
r_ser_rxbit <= '1';
r_ser_rx_bit <= '1';
end if;
-- Bit timer.
@ -323,34 +357,41 @@ begin
end if;
elsif r_ser_rx_state = "01" then
-- Wait for start of byte.
r_ser_rx_shift(7 downto 0) <= (others => '0');
r_ser_rx_shift(8) <= '1';
r_ser_rx_timer <= to_unsigned(serial_bitrate_divider / 2 - 2, 13);
r_ser_rx_timer <= to_unsigned(serial_bitrate_divider / 2 - 2, r_ser_rx_timer'length);
r_ser_rx_timeout <= '0';
if r_ser_rx_bit = '0' then
r_ser_rx_state <= "10";
end if;
elsif r_ser_rx_state = "10" then
-- Check start bit.
r_ser_rx_shift(7 downto 0) <= (others => '1');
r_ser_rx_shift(8) <= '0';
if r_ser_rx_timeout = '1' then
if r_ser_rx_bit = '0' then
r_ser_rx_state <= "11";
else
r_ser_rx_state <= "00";
end if;
r_ser_rx_timer <= to_unsigned(serial_bitrate_divider - 2, r_ser_rx_timer'length);
end if;
elsif r_ser_rx_state = "11" then
-- Wait for data bit.
if r_ser_rx_timeout = '1' then
r_ser_rx_shift <= r_ser_rx_bit & r_ser_rx_shift(8 downto 1);
if r_ser_rx_shift(0) = '1' then
if r_ser_rx_shift(0) = '0' then
-- Reached end of byte.
if r_ser_rx_bit = '1' then
-- Got valid stop bit.
r_ser_rx_byte <= r_ser_rx_shift(8 downto 1);
r_ser_rx_strobe <= '1';
r_ser_rx_state <= "01";
else
-- Got invalid stop bit.
r_ser_rx_state <= "00";
end if;
r_ser_rx_state <= "11";
end if;
r_ser_rx_timer <= to_unsigned(serial_bitrate_divider - 2);
r_ser_rx_timer <= to_unsigned(serial_bitrate_divider - 2, r_ser_rx_timer'length);
end if;
else
-- Invalid state.
r_ser_rx_state <= "00";
end if;
-- Synchronous reset.
@ -382,7 +423,7 @@ begin
if r_ser_tx_busy = '0' then
-- Wait for start of byte.
r_ser_tx_timer <= to_unsigned(serial_bitrate_divider - 2, 13);
r_ser_tx_timer <= to_unsigned(serial_bitrate_divider - 2, r_ser_tx_timer'length);
r_ser_tx_timeout <= '0';
r_ser_tx_shift <= r_ser_tx_byte;
r_ser_tx_bitcnt <= to_unsigned(9, 4);
@ -392,13 +433,13 @@ begin
r_ser_tx_busy <= '1';
end if;
elsif r_ser_tx_busy = '1' and r_ser_tx_timout = '1' then
elsif r_ser_tx_busy = '1' and r_ser_tx_timeout = '1' then
-- Send next bit.
r_ser_tx_bit <= r_ser_tx_shift(0);
r_ser_tx_shift <= "1" & r_ser_tx_shift(7 downto 1);
r_ser_tx_bitcnt <= r_ser_tx_bitcnt - 1;
r_ser_tx_timer <= to_unsigned(serial_bitrate_divider - 2, 13);
r_ser_tx_timer <= to_unsigned(serial_bitrate_divider - 2, r_ser_tx_timer'length);
if r_ser_tx_bitcnt = 0 then
-- Just completed stop bit.
r_ser_tx_busy <= '0';

235
synth/digilent_atlys/ac97out.vhdl Normal file
View File

@ -0,0 +1,235 @@
--
-- Simple core for AC97 audio output.
--
-- Sets output volume to -12 dB,
-- then plays stereo PCM data at 48 kHz sample rate.
-- Only tested with LM4550 on Digilent Atlys board.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ac97out is
port (
-- AC97 bit clock.
bitclk: in std_logic;
-- Asynchronous reset, active low.
resetn: in std_logic;
-- Input samples for left and right channel.
data_left: in signed(19 downto 0);
data_right: in signed(19 downto 0);
-- Data handshake.
data_valid: in std_logic;
data_ready: out std_logic;
-- AC97 interface signals.
ac97_sdi: in std_logic;
ac97_sdo: out std_logic;
ac97_sync: out std_logic );
end entity;
architecture rtl of ac97out is
-- Initialization sequence.
type init_table_type is array(0 to 7) of std_logic_vector(23 downto 0);
constant init_table: init_table_type := (
-- write 0x0000 to register 0x00: soft reset
x"000000",
-- write 0x0000 to register 0x02: set master volume to -12 dB
x"020808",
-- write 0x0000 to register 0x04: set headphone volume to -12 dB
x"040808",
-- write 0x0000 to register 0x06: set mono_out volume to -12 dB
x"060008",
-- write 0x0808 to register 0x18: set PCM out volume to 0 dB
x"180808",
-- dummy read from register 0x00
x"800000",
x"800000",
x"800000" );
-- Output registers.
signal r_ready: std_logic;
signal r_sdo: std_logic;
signal r_sync: std_logic;
-- Reset synchronization.
signal r_rstsync: std_logic_vector(7 downto 0);
-- Bit counter.
signal r_bitcnt: unsigned(7 downto 0);
signal r_lastbit: std_logic;
signal r_endsync: std_logic;
-- Initialization state machine.
signal r_initwait: unsigned(5 downto 0);
signal r_initbusy: std_logic;
signal r_initdone: std_logic;
signal r_initstep: unsigned(2 downto 0);
signal r_initword: std_logic_vector(23 downto 0);
-- Data for next frame.
signal r_datavalid: std_logic;
signal r_dataleft: std_logic_vector(19 downto 0);
signal r_dataright: std_logic_vector(19 downto 0);
-- Frame data shift register (tag + slots 1 .. 4)
signal r_sdoshift: std_logic_vector(95 downto 0);
-- AC97 bit input register
signal r_sdi: std_logic;
begin
-- Drive outputs.
data_ready <= r_ready;
ac97_sdo <= r_sdo;
ac97_sync <= r_sync;
-- Synchronous process.
-- Sample AC97_SDI on falling edge of BITCLK.
process (bitclk) is
begin
if falling_edge(bitclk) then
r_sdi <= ac97_sdi;
end if;
end process;
-- Synchronous process.
process (bitclk, resetn) is
begin
if resetn = '0' then
-- Asynchronous reset.
r_rstsync <= (others => '0');
r_ready <= '0';
-- Outputs to codec must be low during reset.
r_sdo <= '0';
r_sync <= '0';
elsif rising_edge(bitclk) then
-- Drive SYNC high for 16 cycles at start of frame.
if r_lastbit = '1' then
r_sync <= '1';
elsif r_endsync = '1' then
r_sync <= '0';
end if;
-- Push next data bit to output.
r_sdo <= r_sdoshift(r_sdoshift'high);
r_sdoshift <= r_sdoshift(r_sdoshift'high-1 downto 0) & "0";
-- Fetch data from init table.
r_initword <= init_table(to_integer(r_initstep));
-- Prepare next frame.
if r_lastbit = '1' then
-- sdoshift(95:80) = TAG
-- bit 15 = master valid bit
-- bit 14 = slot 1 valid
-- bit 13 = slot 2 valid
-- bit 12 = slot 3 valid
-- bit 11 = slot 4 valid
-- Always set frame valid.
r_sdoshift(95) <= '1';
-- Set slots 1 and 2 valid if we are initializing.
r_sdoshift(94) <= r_initbusy;
r_sdoshift(93) <= r_initbusy;
-- Set slots 3 and 4 valid if we have valid data.
r_sdoshift(92) <= r_datavalid;
r_sdoshift(91) <= r_datavalid;
-- Remaining tag bits always zero.
r_sdoshift(90 downto 80) <= (others => '0');
-- Slot 1: Register read/write command.
-- bit 19 = read (1) or write (0)
-- bit 18:12 = address
r_sdoshift(79 downto 72) <= r_initword(23 downto 16);
r_sdoshift(71 downto 60) <= (others => '0');
-- Slot 2: Register write data.
-- bit 19:4 = data
r_sdoshift(59 downto 44) <= r_initword(15 downto 0);
r_sdoshift(43 downto 40) <= (others => '0');
-- Update init pointer.
if r_initbusy = '1' then
r_initstep <= r_initstep + 1;
end if;
if r_initstep = 7 then
r_initbusy <= '0';
r_initdone <= '1';
end if;
-- Update init delay counter (wait for 1.3 ms after reset).
r_initwait <= r_initwait - 1;
if r_initwait = 0 then
r_initstep <= (others => '0');
r_initbusy <= not r_initdone;
end if;
-- Slots 3 and 4: left and right sample value.
r_sdoshift(39 downto 20) <= r_dataleft;
r_sdoshift(19 downto 0) <= r_dataright;
-- Consume sample values.
r_datavalid <= '0';
r_ready <= '1';
end if;
-- Update bit counter.
r_bitcnt <= r_bitcnt - 1;
if r_bitcnt = 1 then
r_lastbit <= '1';
else
r_lastbit <= '0';
end if;
if r_bitcnt = 241 then
r_endsync <= '1';
else
r_endsync <= '0';
end if;
-- Capture input data.
if r_ready = '1' and data_valid = '1' then
r_ready <= '0';
r_datavalid <= '1';
r_dataleft <= std_logic_vector(data_left);
r_dataright <= std_logic_vector(data_right);
end if;
-- Release synchronous reset.
r_rstsync <= "1" & r_rstsync(7 downto 1);
-- Synchronous reset.
if r_rstsync(0) = '0' then
r_ready <= '0';
r_sdo <= '0';
r_sync <= '0';
r_initbusy <= '0';
r_initdone <= '0';
r_initwait <= (others => '1');
r_initstep <= (others => '0');
r_bitcnt <= (others => '0');
r_datavalid <= '0';
end if;
end if;
end process;
end architecture;

38
synth/digilent_atlys/atlys.ucf Normal file
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@ -0,0 +1,38 @@
# clock pin for Atlys rev C board
NET "clk" LOC = "L15" | IOSTANDARD = LVCMOS33 ;
# 100 MHz
NET "clk" TNM_NET = "clk" ;
TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50% ;
# Reset button
NET "resetn" LOC = "T15" | IOSTANDARD = LVCMOS33 ;
# LEDs
NET "led<0>" LOC = "U18" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ;
NET "led<1>" LOC = "M14" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ;
NET "led<2>" LOC = "N14" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ;
NET "led<3>" LOC = "L14" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ;
NET "led<4>" LOC = "M13" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ;
NET "led<5>" LOC = "D4" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ;
NET "led<6>" LOC = "P16" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ;
NET "led<7>" LOC = "N12" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ;
# USB serial port J17
NET "uartrx" LOC = "A16" | IOSTANDARD = LVCMOS33 ;
NET "uarttx" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
# Audio
NET "ac97_bitclk" LOC = "L13" | IOSTANDARD = LVCMOS33 ;
NET "ac97_sdi" LOC = "T18" | IOSTANDARD = LVCMOS33 ;
NET "ac97_sdo" LOC = "N16" | IOSTANDARD = LVCMOS33 ;
NET "ac97_sync" LOC = "U17" | IOSTANDARD = LVCMOS33 ;
NET "ac97_rst" LOC = "T17" | IOSTANDARD = LVCMOS33 ;
# Constrain bitclk to 20 MHz (actual frequency is 12.288 MHz)
NET "ac97_bitclk" PERIOD = 50 ns HIGH 50% ;
OFFSET = IN 10 ns VALID 20 ns BEFORE "ac97_bitclk" FALLING ;
OFFSET = OUT 15 ns AFTER "ac97_bitclk" RISING ;

191
synth/digilent_atlys/test_sincos.gise Normal file
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@ -0,0 +1,191 @@
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<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="6" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
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<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
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171
synth/digilent_atlys/top_test_sincos.vhdl Normal file
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--
-- Test sine / cosine function core on Digilent Atlys board.
--
--
-- Serial port protocol (via USB):
--
-- * Baud rate 115200
--
-- * Send 6 bytes
-- { 0x41 0x42 phase(7:0) phase(15:8) phase(23:16) phase(31:24) }
-- to calculate sine and cosine of phase on the 18-bit / 20-bit core.
-- Board answers with 8 bytes
-- { sin(7:0) sin(15:8) sin(23:16) sin(31:24)
-- cos(7:0) cos(15:8) cos(23:16) cos(31:24 }
--
-- * Send 6 bytes
-- { 0x41 0x43 phase(7:0) phase(15:8) phase(23:16) phase(31:24) }
-- to calculate sine and cosine of phase on the 24-bit / 26-bit core.
-- Board answers with 8 bytes
-- { sin(7:0) sin(15:8) sin(23:16) sin(31:24)
-- cos(7:0) cos(15:8) cos(23:16) cos(31:24 }
--
-- * Send 2 bytes { 0x41 0x44 } to start clock-enable modulation.
--
-- * Send 3 bytes { 0x41 0x45 } to stop clock-enable modulation.
--
-- Status LEDs:
-- LED 0 = Ready (waiting for command)
-- LED 1 = Calculating
-- LED 2 = Clock-enable modulation active
-- LED 3 = Transmitting
--
-- AC97 audio:
-- 999.985 Hz sine wave on output
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_test_sincos is
port (
-- 100 MHz system clock
clk: in std_logic;
-- Reset button
resetn: in std_logic;
-- Status LEDs
led: out std_logic_vector(7 downto 0);
-- Uart
uartrx: in std_logic;
uarttx: out std_logic;
-- AC97 audio
ac97_bitclk: in std_logic;
ac97_sdi: in std_logic;
ac97_sdo: out std_logic;
ac97_sync: out std_logic;
ac97_rst: out std_logic );
end entity;
architecture rtl of top_test_sincos is
-- Frequency is 21845 / 2**20 * 48000 Hz = 999.985 Hz
constant tone_freq: integer := 21845;
signal r_rstgen: std_logic_vector(7 downto 0) := "00000000";
signal r_reset: std_logic;
signal r_ac97_rstcnt: unsigned(7 downto 0);
signal r_ac97_rst: std_logic;
signal r_ac97_phase: unsigned(19 downto 0);
signal s_ac97_sine: signed(17 downto 0);
signal s_ac97_dataleft: signed(19 downto 0);
signal s_ac97_dataright: signed(19 downto 0);
signal s_ac97_ready: std_logic;
begin
-- Instantiate test design with serial interface.
u0: entity work.test_sincos_serial
generic map (
serial_bitrate_divider => 868 )
port map (
clk => clk,
rst => r_reset,
ser_rx => uartrx,
ser_tx => uarttx,
stat_ready => led(0),
stat_calc => led(1),
stat_clkmod => led(2),
stat_txser => led(3) );
-- Instantiate sine generator for AC97 output.
u1: entity work.sincos_gen_d18_p20
port map (
clk => ac97_bitclk,
clk_en => '1',
in_phase => r_ac97_phase,
out_sin => s_ac97_sine,
out_cos => open );
-- Instantiate AC97 output
u2: entity work.ac97out
port map (
bitclk => ac97_bitclk,
resetn => r_ac97_rst,
data_left => s_ac97_dataleft,
data_right => s_ac97_dataright,
data_valid => '1',
data_ready => s_ac97_ready,
ac97_sdi => ac97_sdi,
ac97_sdo => ac97_sdo,
ac97_sync => ac97_sync );
-- Pad 18-bit signed samples to 20-bit.
s_ac97_dataleft <= s_ac97_sine & "00";
s_ac97_dataright <= s_ac97_sine & "00";
-- Drive unused LEDs.
led(7 downto 4) <= "0000";
-- Drive AC97 reset pin.
ac97_rst <= r_ac97_rst;
-- Reset synchronizer.
process (clk) is
begin
if rising_edge(clk) then
if resetn = '0' then
r_rstgen <= (others => '0');
r_reset <= '1';
else
r_rstgen <= "1" & r_rstgen(7 downto 1);
r_reset <= not r_rstgen(0);
end if;
end if;
end process;
-- Reset generator for AC97 codec.
process (clk) is
begin
if rising_edge(clk) then
if r_reset = '1' then
r_ac97_rstcnt <= (others => '1');
r_ac97_rst <= '0';
else
r_ac97_rstcnt <= r_ac97_rstcnt - 1;
if r_ac97_rstcnt = 0 then
r_ac97_rst <= '1';
end if;
end if;
end if;
end process;
-- Synchronous process in AC97 bitclock domain.
process (ac97_bitclk) is
begin
if rising_edge(ac97_bitclk) then
if s_ac97_ready = '1' then
r_ac97_phase <= r_ac97_phase + tone_freq;
end if;
end if;
end process;
end architecture;

131
tools/test_sincos_serial.py Normal file
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#!/usr/bin/python
"""
Test sine/cosine core via serial port.
Sends a series of commands to the test driver via the serial port
and verifies answers.
Usage:
python test_sincos_serial.py /dev/ttyUSB0
"""
from __future__ import print_function
import sys
import numpy
import serial
import struct
def testPhase(dev, coresel, databits, phasebits, phase):
print("\r phase=%-10d" % phase, end='')
sys.stdout.flush()
dev.write(struct.pack("<BBI", 0x41, 0x42 + coresel, phase))
reply = dev.read(8)
if len(reply) != 8:
print()
print("ERROR: got %d bytes from serial port while expecting 8" %
len(reply))
return
(vsin, vcos) = struct.unpack("<ii", reply)
ampl = (1 << (databits - 1)) - 1
theta = 2 * numpy.pi * phase / 2.0**phasebits
refsin = ampl * numpy.sin(theta)
refcos = ampl * numpy.cos(theta)
if abs(vsin - refsin) > 1.5 or abs(vcos - refcos) > 1.5:
print()
print("phase=%d sin=%d cos=%d refsin=%.2f refcos=%.2f" %
(phase, vsin, vcos, refsin, refcos))
print("ERROR: wrong answer")
def testCore(dev, clkmod, coresel, databits, phasebits):
if clkmod:
# Start clock-enable modulation.
dev.write("AD")
else:
# Stop clock-enable modulation.
dev.write("AE")
print("test least significant phase bits")
for p in range(64):
phase = p
testPhase(dev, coresel, databits, phasebits, phase)
print()
print("test most significant phase bits")
for p in range(64):
phase = p << (phasebits - 6)
testPhase(dev, coresel, databits, phasebits, phase)
print()
print("test pseudorandom phase values")
phase = 0
for i in range(5000):
phase = (phase + 123457) & ((1 << phasebits) - 1)
testPhase(dev, coresel, databits, phasebits, phase)
print()
def main():
if len(sys.argv) != 2:
print(__doc__, file=sys.stderr)
print("ERROR: Invalid/missing command line arguments", file=sys.stderr)
sys.exit(1)
devname = sys.argv[1]
# Open serial port.
print("opening serial port", devname)
dev = serial.Serial(port=devname,
baudrate=115200,
bytesize=8,
parity='N',
stopbits=1,
timeout=1)
# Flush input.
print("flush serial port buffer")
dev.flushInput()
dev.flushOutput()
dev.read(1000)
# Write series of Z to force test driver to idle state.
dev.write("ZZZZZZZZ")
print()
print('Test 18-bit data, 20-bit phase core')
testCore(dev, 0, 0, 18, 20)
print()
print('Test 24-bit data, 26-bit phase core')
testCore(dev, 0, 1, 24, 26)
print()
print('Test 18-bit data, 20-bit phase core with clock-enable modulation')
testCore(dev, 1, 0, 18, 20)
print()
print('Test 24-bit data, 26-bit phase core with clock-enable modulation')
testCore(dev, 1, 1, 24, 26)
print()
# Close serial port.
dev.close()
print("done")
if __name__ == '__main__':
main()