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vhdl-sincos-gen
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* Finally found a way to describe the lookup table such that both 

ISE and Vivado infer a dual-port block RAM.
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Joris van Rantwijk 2016-04-19 22:48:17 +02:00 committed by Joris van Rantwijk
parent 2ed074011e
commit 385c9f5ed2
1 changed files with 7 additions and 3 deletions
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rtl/sincos_gen.vhdl
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@ -98,7 +98,10 @@ architecture rtl of sincos_gen is
-- Lookup table for the first quarter-period of the sine. -- Lookup table for the first quarter-period of the sine.
-- lookup_table[i] == sin( (i + 0.5) / table_size * pi / 2 ) -- lookup_table[i] == sin( (i + 0.5) / table_size * pi / 2 )
constant lookup_table: table_type := gen_table; --
-- Note: This must be a signal, not a constant, otherwise Xilinx
-- tools will not properly infer block RAM.
signal lookup_table: table_type := gen_table;
-- Internal registers. -- Internal registers.
signal r1_quadrant: unsigned(1 downto 0); signal r1_quadrant: unsigned(1 downto 0);
@ -156,9 +159,10 @@ architecture rtl of sincos_gen is
signal r_outcos: signed(data_bits-1 downto 0); signal r_outcos: signed(data_bits-1 downto 0);
-- Attributes for Xilinx synthesis. -- Attributes for Xilinx synthesis.
-- Note: This is necessary, otherwise Vivado will not properly
-- infer block RAM.
attribute rom_style: string; attribute rom_style: string;
attribute rom_style of r2_sin_data: signal is "block"; attribute rom_style of lookup_table: signal is "block";
attribute rom_style of r2_cos_data: signal is "block";
begin begin