vhdl-sincos-gen/synth/xilinx_spartan6/sincos_gen_d18_p20.ucf

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2016-04-19 23:20:07 +02:00
#Created by Constraints Editor (xc6slx45-csg324-2) - 2016/04/19
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 4 ns HIGH 50%;