From e402b88b3d64f998df6b624fe9ef62c921b9d927 Mon Sep 17 00:00:00 2001
From: Joris van Rantwijk <joris@jorisvr.nl>
Date: Fri, 22 Apr 2016 21:06:40 +0200
Subject: [PATCH] Minor change to atlys toplevel.

* Rename .vhd -> .vhdl
* Reset phase of audio tone.
---
 synth/digilent_atlys/test_sincos.gise         | 22 +++++++++----------
 synth/digilent_atlys/test_sincos.xise         |  4 ++--
 ...p_test_sincos.vhd => top_test_sincos.vhdl} |  1 +
 3 files changed, 14 insertions(+), 13 deletions(-)
 rename synth/digilent_atlys/{top_test_sincos.vhd => top_test_sincos.vhdl} (99%)

diff --git a/synth/digilent_atlys/test_sincos.gise b/synth/digilent_atlys/test_sincos.gise
index 59a6dac..37c1a56 100644
--- a/synth/digilent_atlys/test_sincos.gise
+++ b/synth/digilent_atlys/test_sincos.gise
@@ -79,11 +79,11 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461310404" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1544048785962338122" xil_pn:start_ts="1461310404">
+    <transform xil_pn:end_ts="1461346674" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1544048785962338122" xil_pn:start_ts="1461346674">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461310404" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6687268679030817511" xil_pn:start_ts="1461310404">
+    <transform xil_pn:end_ts="1461346674" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6687268679030817511" xil_pn:start_ts="1461346674">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
@@ -91,7 +91,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461310404" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1379793326671312440" xil_pn:start_ts="1461310404">
+    <transform xil_pn:end_ts="1461346674" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1379793326671312440" xil_pn:start_ts="1461346674">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
@@ -99,11 +99,11 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461310404" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3262842109162067599" xil_pn:start_ts="1461310404">
+    <transform xil_pn:end_ts="1461346674" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3262842109162067599" xil_pn:start_ts="1461346674">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461346115" xil_pn:in_ck="-8881070640450067642" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8668749107623387584" xil_pn:start_ts="1461346100">
+    <transform xil_pn:end_ts="1461346689" xil_pn:in_ck="2072574044500593778" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8668749107623387584" xil_pn:start_ts="1461346674">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -121,11 +121,11 @@
       <outfile xil_pn:name="webtalk_pn.xml"/>
       <outfile xil_pn:name="xst"/>
     </transform>
-    <transform xil_pn:end_ts="1461310450" xil_pn:in_ck="141509727442713" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="7075349975164966765" xil_pn:start_ts="1461310450">
+    <transform xil_pn:end_ts="1461346689" xil_pn:in_ck="141509727442713" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="7075349975164966765" xil_pn:start_ts="1461346689">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461346125" xil_pn:in_ck="-1047380743607608193" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="392032481918333458" xil_pn:start_ts="1461346118">
+    <transform xil_pn:end_ts="1461346696" xil_pn:in_ck="-1047380743607608193" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="392032481918333458" xil_pn:start_ts="1461346689">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_ngo"/>
@@ -134,7 +134,7 @@
       <outfile xil_pn:name="top_test_sincos.ngd"/>
       <outfile xil_pn:name="top_test_sincos_ngdbuild.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1461346156" xil_pn:in_ck="-1047380743607608192" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4245753365082497697" xil_pn:start_ts="1461346125">
+    <transform xil_pn:end_ts="1461346726" xil_pn:in_ck="-1047380743607608192" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4245753365082497697" xil_pn:start_ts="1461346696">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -148,7 +148,7 @@
       <outfile xil_pn:name="top_test_sincos_summary.xml"/>
       <outfile xil_pn:name="top_test_sincos_usage.xml"/>
     </transform>
-    <transform xil_pn:end_ts="1461346184" xil_pn:in_ck="693365441136831385" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1461346156">
+    <transform xil_pn:end_ts="1461346754" xil_pn:in_ck="693365441136831385" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1461346726">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -163,7 +163,7 @@
       <outfile xil_pn:name="top_test_sincos_pad.txt"/>
       <outfile xil_pn:name="top_test_sincos_par.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1461346232" xil_pn:in_ck="4016941542054796675" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="97434230493978268" xil_pn:start_ts="1461346215">
+    <transform xil_pn:end_ts="1461346939" xil_pn:in_ck="4016941542054796675" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="97434230493978268" xil_pn:start_ts="1461346923">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -176,7 +176,7 @@
       <outfile xil_pn:name="webtalk.log"/>
       <outfile xil_pn:name="webtalk_pn.xml"/>
     </transform>
-    <transform xil_pn:end_ts="1461346184" xil_pn:in_ck="-1047380743607608324" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1461346176">
+    <transform xil_pn:end_ts="1461346754" xil_pn:in_ck="-1047380743607608324" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1461346746">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
diff --git a/synth/digilent_atlys/test_sincos.xise b/synth/digilent_atlys/test_sincos.xise
index 714ab01..c7924ce 100644
--- a/synth/digilent_atlys/test_sincos.xise
+++ b/synth/digilent_atlys/test_sincos.xise
@@ -15,7 +15,7 @@
   <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
 
   <files>
-    <file xil_pn:name="top_test_sincos.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="top_test_sincos.vhdl" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
@@ -158,7 +158,7 @@
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top_test_sincos|rtl" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="top_test_sincos.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="top_test_sincos.vhdl" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top_test_sincos" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
diff --git a/synth/digilent_atlys/top_test_sincos.vhd b/synth/digilent_atlys/top_test_sincos.vhdl
similarity index 99%
rename from synth/digilent_atlys/top_test_sincos.vhd
rename to synth/digilent_atlys/top_test_sincos.vhdl
index 3a7bcd1..85cda59 100644
--- a/synth/digilent_atlys/top_test_sincos.vhd
+++ b/synth/digilent_atlys/top_test_sincos.vhdl
@@ -161,6 +161,7 @@ begin
     begin
         if r_ac97_rst = '0' then
             r_ac97_rstsync  <= (others => '1');
+            r_ac97_phase    <= (others => '0');
         elsif rising_edge(ac97_bitclk) then
             r_ac97_rstsync  <= "0" & r_ac97_rstsync(7 downto 1);
             if s_ac97_ready = '1' then