diff --git a/synth/digilent_atlys/test_sincos.gise b/synth/digilent_atlys/test_sincos.gise
index 59a6dac..37c1a56 100644
--- a/synth/digilent_atlys/test_sincos.gise
+++ b/synth/digilent_atlys/test_sincos.gise
@@ -79,11 +79,11 @@
-
+
-
+
@@ -91,7 +91,7 @@
-
+
@@ -99,11 +99,11 @@
-
+
-
+
@@ -121,11 +121,11 @@
-
+
-
+
@@ -134,7 +134,7 @@
-
+
@@ -148,7 +148,7 @@
-
+
@@ -163,7 +163,7 @@
-
+
@@ -176,7 +176,7 @@
-
+
diff --git a/synth/digilent_atlys/test_sincos.xise b/synth/digilent_atlys/test_sincos.xise
index 714ab01..c7924ce 100644
--- a/synth/digilent_atlys/test_sincos.xise
+++ b/synth/digilent_atlys/test_sincos.xise
@@ -15,7 +15,7 @@
-
+
@@ -158,7 +158,7 @@
-
+
diff --git a/synth/digilent_atlys/top_test_sincos.vhd b/synth/digilent_atlys/top_test_sincos.vhdl
similarity index 99%
rename from synth/digilent_atlys/top_test_sincos.vhd
rename to synth/digilent_atlys/top_test_sincos.vhdl
index 3a7bcd1..85cda59 100644
--- a/synth/digilent_atlys/top_test_sincos.vhd
+++ b/synth/digilent_atlys/top_test_sincos.vhdl
@@ -161,6 +161,7 @@ begin
begin
if r_ac97_rst = '0' then
r_ac97_rstsync <= (others => '1');
+ r_ac97_phase <= (others => '0');
elsif rising_edge(ac97_bitclk) then
r_ac97_rstsync <= "0" & r_ac97_rstsync(7 downto 1);
if s_ac97_ready = '1' then