From 9c73463282349e0542bb89131576104930a9e136 Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Fri, 22 Apr 2016 09:42:48 +0200 Subject: [PATCH] Add top-level test design for Digilent Atlys board. --- synth/digilent_atlys/atlys.ucf | 38 +++ synth/digilent_atlys/test_sincos.gise | 189 ++++++++++ synth/digilent_atlys/test_sincos.xise | 418 +++++++++++++++++++++++ synth/digilent_atlys/top_test_sincos.vhd | 110 ++++++ 4 files changed, 755 insertions(+) create mode 100644 synth/digilent_atlys/atlys.ucf create mode 100644 synth/digilent_atlys/test_sincos.gise create mode 100644 synth/digilent_atlys/test_sincos.xise create mode 100644 synth/digilent_atlys/top_test_sincos.vhd diff --git a/synth/digilent_atlys/atlys.ucf b/synth/digilent_atlys/atlys.ucf new file mode 100644 index 0000000..82f36d2 --- /dev/null +++ b/synth/digilent_atlys/atlys.ucf @@ -0,0 +1,38 @@ + +# clock pin for Atlys rev C board +NET "clk" LOC = "L15" | IOSTANDARD = LVCMOS33 ; + +# 100 MHz +NET "clk" TNM_NET = "clk" ; +TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50% ; + +# Reset button +NET "resetn" LOC = "T15" | IOSTANDARD = LVCMOS18 ; + +# LEDs +NET "led<0>" LOC = "U18" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ; +NET "led<1>" LOC = "M14" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ; +NET "led<2>" LOC = "N14" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ; +NET "led<3>" LOC = "L14" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ; +NET "led<4>" LOC = "M13" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ; +NET "led<5>" LOC = "D4" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ; +NET "led<6>" LOC = "P16" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ; +NET "led<7>" LOC = "N12" | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO ; + +# USB serial port J17 +NET "uartrx" LOC = "A16" | IOSTANDARD = LVCMOS33 ; +NET "uarttx" LOC = "B16" | IOSTANDARD = LVCMOS33 ; + +# Audio +NET "ac97_bitclk" LOC = "L13" | IOSTANDARD = LVCMOS33 ; +NET "ac97_sdi" LOC = "T18" | IOSTANDARD = LVCMOS33 ; +NET "ac97_sdo" LOC = "N16" | IOSTANDARD = LVCMOS33 ; +NET "ac97_sync" LOC = "U17" | IOSTANDARD = LVCMOS33 ; +NET "ac97_rst" LOC = "T17" | IOSTANDARD = LVCMOS33 ; + +# Constrain bitclk to 20 MHz (actual frequency is 12.288 MHz) +NET "ac97_bitclk" PERIOD = 50 ns HIGH 50% ; + +OFFSET = IN 10 ns VALID 20 ns BEFORE "ac97_bitclk" FALLING ; +OFFSET = OUT 15 ns AFTER "ac97_bitclk" RISING ; + diff --git a/synth/digilent_atlys/test_sincos.gise b/synth/digilent_atlys/test_sincos.gise new file mode 100644 index 0000000..37d03a4 --- /dev/null +++ b/synth/digilent_atlys/test_sincos.gise @@ -0,0 +1,189 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/synth/digilent_atlys/test_sincos.xise b/synth/digilent_atlys/test_sincos.xise new file mode 100644 index 0000000..0fdf5c1 --- /dev/null +++ b/synth/digilent_atlys/test_sincos.xise @@ -0,0 +1,418 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/synth/digilent_atlys/top_test_sincos.vhd b/synth/digilent_atlys/top_test_sincos.vhd new file mode 100644 index 0000000..6c780b3 --- /dev/null +++ b/synth/digilent_atlys/top_test_sincos.vhd @@ -0,0 +1,110 @@ +-- +-- Test sine / cosine function core on Digilent Atlys board. +-- +-- +-- Serial port protocol (via USB): +-- +-- * Baud rate 115200 +-- +-- * Send 6 bytes +-- { 0x41 0x42 phase(7:0) phase(15:8) phase(23:16) phase(31:24) } +-- to calculate sine and cosine of phase on the 18-bit / 20-bit core. +-- Board answers with 8 bytes +-- { sin(7:0) sin(15:8) sin(23:16) sin(31:24) +-- cos(7:0) cos(15:8) cos(23:16) cos(31:24 } +-- +-- * Send 6 bytes +-- { 0x41 0x43 phase(7:0) phase(15:8) phase(23:16) phase(31:24) } +-- to calculate sine and cosine of phase on the 24-bit / 26-bit core. +-- Board answers with 8 bytes +-- { sin(7:0) sin(15:8) sin(23:16) sin(31:24) +-- cos(7:0) cos(15:8) cos(23:16) cos(31:24 } +-- +-- * Send 2 bytes { 0x41 0x44 } to start clock-enable modulation. +-- +-- * Send 3 bytes { 0x41 0x45 } to stop clock-enable modulation. +-- +-- Status LEDs: +-- LED 0 = Ready (waiting for command) +-- LED 1 = Calculating +-- LED 2 = Clock-enable modulation active +-- LED 3 = Transmitting +-- +-- AC97 audio: +-- not yet implemented +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity top_test_sincos is + + port ( + -- 100 MHz system clock + clk: in std_logic; + + -- Reset button + resetn: in std_logic; + + -- Status LEDs + led: out std_logic_vector(7 downto 0); + + -- Uart + uartrx: in std_logic; + uarttx: out std_logic; + + -- AC97 audio + ac97_bitclk: in std_logic; + ac97_sdi: in std_logic; + ac97_sdo: out std_logic; + ac97_sync: out std_logic; + ac97_rst: out std_logic ); + +end entity; + +architecture rtl of top_test_sincos is + + signal r_rstgen: std_logic_vector(7 downto 0) := "00000000"; + signal r_reset: std_logic; + +begin + + -- Instantiate test design with serial interface. + u0: entity work.test_sincos_serial + generic map ( + serial_bitrate_divider => 868 ) + port map ( + clk => clk, + rst => r_reset, + ser_rx => uartrx, + ser_tx => uarttx, + stat_ready => led(0), + stat_calc => led(1), + stat_clkmod => led(2), + stat_txser => led(3) ); + + -- Drive unused LEDs. + led(7 downto 4) <= "0000"; + + -- AC97 not yet implemented + ac97_sdo <= '0'; + ac97_sync <= '0'; + ac97_rst <= '0'; + + -- Reset synchronizer. + process (clk) is + begin + if rising_edge(clk) then + if resetn = '0' then + r_rstgen <= (others => '0'); + r_reset <= '1'; + else + r_rstgen <= "1" & r_rstgen(7 downto 1); + r_reset <= not r_rstgen(0); + end if; + end if; + end process; + +end architecture; +