diff --git a/synth/xilinx_spartan6/sincos.gise b/synth/xilinx_spartan6/sincos.gise
index 690444a..7131a04 100644
--- a/synth/xilinx_spartan6/sincos.gise
+++ b/synth/xilinx_spartan6/sincos.gise
@@ -28,6 +28,85 @@
     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="sincos_gen_d18_p20.bld"/>
+    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="sincos_gen_d18_p20.cmd_log"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="sincos_gen_d18_p20.lso"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="sincos_gen_d18_p20.ncd" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="sincos_gen_d18_p20.ngc"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="sincos_gen_d18_p20.ngd"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="sincos_gen_d18_p20.ngr"/>
+    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="sincos_gen_d18_p20.pad"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="sincos_gen_d18_p20.par" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="sincos_gen_d18_p20.pcf" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="sincos_gen_d18_p20.prj"/>
+    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="sincos_gen_d18_p20.ptwx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="sincos_gen_d18_p20.stx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="sincos_gen_d18_p20.syr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="sincos_gen_d18_p20.twr" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="sincos_gen_d18_p20.twx" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="sincos_gen_d18_p20.unroutes" xil_pn:subbranch="Par"/>
+    <file xil_pn:fileType="FILE_XPI" xil_pn:name="sincos_gen_d18_p20.xpi"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="sincos_gen_d18_p20.xst"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="sincos_gen_d18_p20_envsettings.html"/>
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="sincos_gen_d18_p20_guide.ncd" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="sincos_gen_d18_p20_map.map" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="sincos_gen_d18_p20_map.mrp" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="sincos_gen_d18_p20_map.ncd" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="sincos_gen_d18_p20_map.ngm" xil_pn:subbranch="Map"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sincos_gen_d18_p20_map.xrpt"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sincos_gen_d18_p20_ngdbuild.xrpt"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="sincos_gen_d18_p20_pad.csv" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="sincos_gen_d18_p20_pad.txt" xil_pn:subbranch="Par"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sincos_gen_d18_p20_par.xrpt"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="sincos_gen_d18_p20_summary.html"/>
+    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="sincos_gen_d18_p20_summary.xml"/>
+    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="sincos_gen_d18_p20_usage.xml"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sincos_gen_d18_p20_xst.xrpt"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="sincos_gen_d24_p26.bld"/>
+    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="sincos_gen_d24_p26.cmd_log"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="sincos_gen_d24_p26.lso"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="sincos_gen_d24_p26.ncd" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="sincos_gen_d24_p26.ngc"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="sincos_gen_d24_p26.ngd"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="sincos_gen_d24_p26.ngr"/>
+    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="sincos_gen_d24_p26.pad"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="sincos_gen_d24_p26.par" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="sincos_gen_d24_p26.pcf" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="sincos_gen_d24_p26.prj"/>
+    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="sincos_gen_d24_p26.ptwx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="sincos_gen_d24_p26.stx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="sincos_gen_d24_p26.syr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="sincos_gen_d24_p26.twr" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="sincos_gen_d24_p26.twx" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="sincos_gen_d24_p26.unroutes" xil_pn:subbranch="Par"/>
+    <file xil_pn:fileType="FILE_XPI" xil_pn:name="sincos_gen_d24_p26.xpi"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="sincos_gen_d24_p26.xst"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="sincos_gen_d24_p26_envsettings.html"/>
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="sincos_gen_d24_p26_guide.ncd" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="sincos_gen_d24_p26_map.map" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="sincos_gen_d24_p26_map.mrp" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="sincos_gen_d24_p26_map.ncd" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="sincos_gen_d24_p26_map.ngm" xil_pn:subbranch="Map"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sincos_gen_d24_p26_map.xrpt"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sincos_gen_d24_p26_ngdbuild.xrpt"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="sincos_gen_d24_p26_pad.csv" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="sincos_gen_d24_p26_pad.txt" xil_pn:subbranch="Par"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sincos_gen_d24_p26_par.xrpt"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="sincos_gen_d24_p26_summary.html"/>
+    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="sincos_gen_d24_p26_summary.xml"/>
+    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="sincos_gen_d24_p26_usage.xml"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sincos_gen_d24_p26_xst.xrpt"/>
+    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="sincos_table_rom.cmd_log"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="sincos_table_rom.lso"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="sincos_table_rom.ngc"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="sincos_table_rom.ngr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="sincos_table_rom.prj"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="sincos_table_rom.stx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="sincos_table_rom.syr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="sincos_table_rom.xst"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="sincos_table_rom_envsettings.html"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="sincos_table_rom_summary.html"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="sincos_table_rom_xst.xrpt"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="top_d18_p20.bld"/>
     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="top_d18_p20.cmd_log"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="top_d18_p20.lso"/>
@@ -35,17 +114,14 @@
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="top_d18_p20.ngc"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="top_d18_p20.ngd"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="top_d18_p20.ngr"/>
-    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="top_d18_p20.pad"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="top_d18_p20.par" xil_pn:subbranch="Par"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="top_d18_p20.pcf" xil_pn:subbranch="Map"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="top_d18_p20.prj"/>
-    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="top_d18_p20.ptwx"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="top_d18_p20.stx"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="top_d18_p20.syr"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="top_d18_p20.twr" xil_pn:subbranch="Par"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="top_d18_p20.twx" xil_pn:subbranch="Par"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="top_d18_p20.unroutes" xil_pn:subbranch="Par"/>
-    <file xil_pn:fileType="FILE_XPI" xil_pn:name="top_d18_p20.xpi"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="top_d18_p20.xst"/>
     <file xil_pn:fileType="FILE_HTML" xil_pn:name="top_d18_p20_envsettings.html"/>
     <file xil_pn:fileType="FILE_NCD" xil_pn:name="top_d18_p20_guide.ncd" xil_pn:origination="imported"/>
@@ -53,14 +129,9 @@
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_d18_p20_map.mrp" xil_pn:subbranch="Map"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top_d18_p20_map.ncd" xil_pn:subbranch="Map"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="top_d18_p20_map.ngm" xil_pn:subbranch="Map"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_d18_p20_map.xrpt"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_d18_p20_ngdbuild.xrpt"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="top_d18_p20_pad.csv" xil_pn:subbranch="Par"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="top_d18_p20_pad.txt" xil_pn:subbranch="Par"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_d18_p20_par.xrpt"/>
     <file xil_pn:fileType="FILE_HTML" xil_pn:name="top_d18_p20_summary.html"/>
-    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="top_d18_p20_summary.xml"/>
-    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="top_d18_p20_usage.xml"/>
     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_d18_p20_xst.xrpt"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="top_d24_p26.bld"/>
     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="top_d24_p26.cmd_log"/>
@@ -95,103 +166,97 @@
   <transforms xmlns="http://www.xilinx.com/XMLSchema">
     <transform xil_pn:end_ts="1461013719" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1461013719">
       <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461014911" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-639073431793474202" xil_pn:start_ts="1461014911">
+    <transform xil_pn:end_ts="1461100564" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4379833923123898981" xil_pn:start_ts="1461100564">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461014911" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2896311849871758697" xil_pn:start_ts="1461014911">
+    <transform xil_pn:end_ts="1461100564" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4021805998389114860" xil_pn:start_ts="1461100564">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461014911" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1461014911">
+    <transform xil_pn:end_ts="1461100564" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1461100564">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461014911" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1119122686137323032" xil_pn:start_ts="1461014911">
+    <transform xil_pn:end_ts="1461100564" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2920076057229657123" xil_pn:start_ts="1461100564">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461014911" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1461014911">
+    <transform xil_pn:end_ts="1461100564" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1461100564">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461014911" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-695365078470550495" xil_pn:start_ts="1461014911">
+    <transform xil_pn:end_ts="1461100564" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-1422464503374558666" xil_pn:start_ts="1461100564">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461014918" xil_pn:in_ck="3799138003015592937" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="5618403509865248112" xil_pn:start_ts="1461014911">
+    <transform xil_pn:end_ts="1461100571" xil_pn:in_ck="6237691873111016398" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2620952819151134725" xil_pn:start_ts="1461100564">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
-      <outfile xil_pn:name="top_d18_p20.lso"/>
-      <outfile xil_pn:name="top_d18_p20.ngc"/>
-      <outfile xil_pn:name="top_d18_p20.ngr"/>
-      <outfile xil_pn:name="top_d18_p20.prj"/>
-      <outfile xil_pn:name="top_d18_p20.stx"/>
-      <outfile xil_pn:name="top_d18_p20.syr"/>
-      <outfile xil_pn:name="top_d18_p20.xst"/>
-      <outfile xil_pn:name="top_d18_p20_xst.xrpt"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.lso"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.ngc"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.ngr"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.prj"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.stx"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.syr"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.xst"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_xst.xrpt"/>
       <outfile xil_pn:name="webtalk_pn.xml"/>
       <outfile xil_pn:name="xst"/>
     </transform>
-    <transform xil_pn:end_ts="1461015333" xil_pn:in_ck="-1951822929293246800" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-1880473407778747107" xil_pn:start_ts="1461015333">
+    <transform xil_pn:end_ts="1461100571" xil_pn:in_ck="7367196564826055089" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-6756878091118191246" xil_pn:start_ts="1461100571">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1461015337" xil_pn:in_ck="525784713602536255" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8792393459043509058" xil_pn:start_ts="1461015333">
+    <transform xil_pn:end_ts="1461100575" xil_pn:in_ck="-4712295735511276190" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="3858354792276142743" xil_pn:start_ts="1461100571">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_ngo"/>
       <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
-      <outfile xil_pn:name="top_d18_p20.bld"/>
-      <outfile xil_pn:name="top_d18_p20.ngd"/>
-      <outfile xil_pn:name="top_d18_p20_ngdbuild.xrpt"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.bld"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.ngd"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_ngdbuild.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1461015351" xil_pn:in_ck="-370563571678911743" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4245753365082497697" xil_pn:start_ts="1461015337">
+    <transform xil_pn:end_ts="1461100589" xil_pn:in_ck="8453365223204692366" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4245753365082497697" xil_pn:start_ts="1461100575">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
-      <outfile xil_pn:name="top_d18_p20.pcf"/>
-      <outfile xil_pn:name="top_d18_p20_map.map"/>
-      <outfile xil_pn:name="top_d18_p20_map.mrp"/>
-      <outfile xil_pn:name="top_d18_p20_map.ncd"/>
-      <outfile xil_pn:name="top_d18_p20_map.ngm"/>
-      <outfile xil_pn:name="top_d18_p20_map.xrpt"/>
-      <outfile xil_pn:name="top_d18_p20_summary.xml"/>
-      <outfile xil_pn:name="top_d18_p20_usage.xml"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.pcf"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_map.map"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_map.mrp"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_map.ncd"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_map.ngm"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_map.xrpt"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_summary.xml"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_usage.xml"/>
     </transform>
-    <transform xil_pn:end_ts="1461015369" xil_pn:in_ck="-5039478398034442765" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1461015351">
+    <transform xil_pn:end_ts="1461100607" xil_pn:in_ck="6682508134343866937" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1461100589">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
-      <outfile xil_pn:name="top_d18_p20.ncd"/>
-      <outfile xil_pn:name="top_d18_p20.pad"/>
-      <outfile xil_pn:name="top_d18_p20.par"/>
-      <outfile xil_pn:name="top_d18_p20.ptwx"/>
-      <outfile xil_pn:name="top_d18_p20.unroutes"/>
-      <outfile xil_pn:name="top_d18_p20.xpi"/>
-      <outfile xil_pn:name="top_d18_p20_pad.csv"/>
-      <outfile xil_pn:name="top_d18_p20_pad.txt"/>
-      <outfile xil_pn:name="top_d18_p20_par.xrpt"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.ncd"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.pad"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.par"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.ptwx"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.unroutes"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.xpi"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_pad.csv"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_pad.txt"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20_par.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1461015369" xil_pn:in_ck="7266945643214914297" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1461015364">
+    <transform xil_pn:end_ts="1461100607" xil_pn:in_ck="-6631160144728170878" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1461100602">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
-      <outfile xil_pn:name="top_d18_p20.twr"/>
-      <outfile xil_pn:name="top_d18_p20.twx"/>
-    </transform>
-    <transform xil_pn:end_ts="1461015323" xil_pn:in_ck="8147599038285578597" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1461015317">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForInputs"/>
-      <status xil_pn:value="InputAdded"/>
-      <status xil_pn:value="InputChanged"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.twr"/>
+      <outfile xil_pn:name="sincos_gen_d18_p20.twx"/>
     </transform>
   </transforms>
 
diff --git a/synth/xilinx_spartan6/sincos.xise b/synth/xilinx_spartan6/sincos.xise
index 5cd210a..20f8fed 100644
--- a/synth/xilinx_spartan6/sincos.xise
+++ b/synth/xilinx_spartan6/sincos.xise
@@ -15,14 +15,6 @@
   <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
 
   <files>
-    <file xil_pn:name="top_d18_p20.vhdl" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
-    </file>
-    <file xil_pn:name="top_d24_p26.vhdl" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="../../rtl/sincos_gen_d18_p20.vhdl" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
@@ -35,19 +27,14 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
-    <file xil_pn:name="timing.ucf" xil_pn:type="FILE_UCF">
+    <file xil_pn:name="sincos_gen_d18_p20.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="top_d18_p20.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
-    </file>
   </files>
 
   <properties>
     <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -61,8 +48,6 @@
     <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
     <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -79,56 +64,45 @@
     <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
     <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
     <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
     <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
     <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
     <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -136,12 +110,10 @@
     <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
     <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
     <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
     <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -168,18 +140,15 @@
     <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top_d18_p20|rtl" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="top_d18_p20.vhdl" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top_d18_p20" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|sincos_gen_d18_p20|rtl" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../rtl/sincos_gen_d18_p20.vhdl" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/sincos_gen_d18_p20" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -191,7 +160,6 @@
     <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -212,7 +180,6 @@
     <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
     <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
     <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
     <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
@@ -224,7 +191,6 @@
     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
@@ -245,7 +211,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="top_d18_p20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="sincos_gen_d18_p20" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -256,17 +222,14 @@
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
     <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_d18_p20_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="top_d18_p20_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_d18_p20_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_d18_p20_translate.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="sincos_gen_d18_p20_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="sincos_gen_d18_p20_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="sincos_gen_d18_p20_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="sincos_gen_d18_p20_translate.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
@@ -284,11 +247,10 @@
     <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="top_d18_p20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="sincos_gen_d18_p20" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -309,7 +271,6 @@
     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
@@ -317,12 +278,10 @@
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
@@ -337,8 +296,6 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@@ -364,28 +321,21 @@
     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
     <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
     <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
     <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -408,8 +358,7 @@
   </properties>
 
   <bindings>
-    <binding xil_pn:location="/top_d24_p26" xil_pn:name="timing.ucf"/>
-    <binding xil_pn:location="/top_d18_p20" xil_pn:name="top_d18_p20.ucf"/>
+    <binding xil_pn:location="/sincos_gen_d18_p20" xil_pn:name="sincos_gen_d18_p20.ucf"/>
   </bindings>
 
   <libraries/>
diff --git a/synth/xilinx_spartan6/top_d18_p20.ucf b/synth/xilinx_spartan6/sincos_gen_d18_p20.ucf
similarity index 52%
rename from synth/xilinx_spartan6/top_d18_p20.ucf
rename to synth/xilinx_spartan6/sincos_gen_d18_p20.ucf
index fca92a9..5b289cd 100644
--- a/synth/xilinx_spartan6/top_d18_p20.ucf
+++ b/synth/xilinx_spartan6/sincos_gen_d18_p20.ucf
@@ -1,4 +1,4 @@
 
-#Created by Constraints Editor (xc6slx45-csg324-3) - 2016/04/18
+#Created by Constraints Editor (xc6slx45-csg324-2) - 2016/04/19
 NET "clk" TNM_NET = clk;
 TIMESPEC TS_clk = PERIOD "clk" 4 ns HIGH 50%;
diff --git a/synth/xilinx_spartan6/timing.ucf b/synth/xilinx_spartan6/timing.ucf
deleted file mode 100644
index d3c9598..0000000
--- a/synth/xilinx_spartan6/timing.ucf
+++ /dev/null
@@ -1,2 +0,0 @@
-NET "clk" TNM_NET = "clk" ;
-TIMESPEC "TS_clk" = PERIOD "clk" 4 ns ;
diff --git a/synth/xilinx_spartan6/top_d18_p20.vhdl b/synth/xilinx_spartan6/top_d18_p20.vhdl
deleted file mode 100644
index 2af32f7..0000000
--- a/synth/xilinx_spartan6/top_d18_p20.vhdl
+++ /dev/null
@@ -1,45 +0,0 @@
---
---  Top-level design for synthesis dry-run of the sine / cosine function core.
---
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity top_d18_p20 is
-    port (
-        clk:        in  std_logic;
-        clk_en:     in  std_logic;
-        in_phase:   in  std_logic_vector(19 downto 0);
-        out_sin:    out std_logic_vector(17 downto 0);
-        out_cos:    out std_logic_vector(17 downto 0) );
-end entity;
-
-architecture rtl of top_d18_p20 is
-
-    signal r_in_phase:  unsigned(19 downto 0);
-    signal s_out_sin:   signed(17 downto 0);
-    signal s_out_cos:   signed(17 downto 0);
-
-begin
-
-    -- Instantiate core.
-    gen0: entity work.sincos_gen_d18_p20
-        port map (
-            clk             => clk,
-            clk_en          => clk_en,
-            in_phase        => r_in_phase,
-            out_sin         => s_out_sin,
-            out_cos         => s_out_cos );
-
-    -- Input/output flip-flops.
-    process (clk) is
-    begin
-        if rising_edge(clk) then
-            r_in_phase  <= unsigned(in_phase);
-            out_sin     <= std_logic_vector(s_out_sin);
-            out_cos     <= std_logic_vector(s_out_cos);
-        end if;
-    end process;
-
-end architecture;
diff --git a/synth/xilinx_spartan6/top_d24_p26.vhdl b/synth/xilinx_spartan6/top_d24_p26.vhdl
deleted file mode 100644
index a064243..0000000
--- a/synth/xilinx_spartan6/top_d24_p26.vhdl
+++ /dev/null
@@ -1,45 +0,0 @@
---
---  Top-level design for synthesis dry-run of the sine / cosine function core.
---
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity top_d24_p26 is
-    port (
-        clk:        in  std_logic;
-        clk_en:     in  std_logic;
-        in_phase:   in  std_logic_vector(25 downto 0);
-        out_sin:    out std_logic_vector(23 downto 0);
-        out_cos:    out std_logic_vector(23 downto 0) );
-end entity;
-
-architecture rtl of top_d24_p26 is
-
-    signal r_in_phase:  unsigned(25 downto 0);
-    signal s_out_sin:   signed(23 downto 0);
-    signal s_out_cos:   signed(23 downto 0);
-
-begin
-
-    -- Instantiate core.
-    gen0: entity work.sincos_gen_d24_p26
-        port map (
-            clk             => clk,
-            clk_en          => clk_en,
-            in_phase        => r_in_phase,
-            out_sin         => s_out_sin,
-            out_cos         => s_out_cos );
-
-    -- Input/output flip-flops.
-    process (clk) is
-    begin
-        if rising_edge(clk) then
-            r_in_phase  <= unsigned(in_phase);
-            out_sin     <= std_logic_vector(s_out_sin);
-            out_cos     <= std_logic_vector(s_out_cos);
-        end if;
-    end process;
-
-end architecture;