diff --git a/rtl/sincos_gen_d18_p20.vhdl b/rtl/sincos_gen_d18_p20.vhdl
index 8feba07..1754d80 100644
--- a/rtl/sincos_gen_d18_p20.vhdl
+++ b/rtl/sincos_gen_d18_p20.vhdl
@@ -7,6 +7,9 @@
 --  Sin/cos output:
 --    signed 18 bits (nominal amplitude = 2**17-1)
 --
+--  Latency:
+--    6 clock cycles
+--
 --  Copyright 2016 Joris van Rantwijk
 --
 --  This design is free software; you can redistribute it and/or