vhdl-sincos-gen/synth/xilinx_spartan6/sincos_gen_d18_p20.ucf

#Created by Constraints Editor (xc6slx45-csg324-2) - 2016/04/19
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 4 ns HIGH 50%;