221 lines
10 KiB
VHDL
221 lines
10 KiB
VHDL
--
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-- Global definitions for Red Pitaya PuzzleFW firmware.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package puzzlefw_pkg is
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-- 32-bit address for DMA on AXI bus, aligned to 8-byte multiple.
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subtype dma_address_type is std_logic_vector(31 downto 3);
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type dma_address_array is array(natural range <>) of dma_address_type;
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-- Burst length for DMA on AXI bus as number of beats minus 1.
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subtype dma_burst_length_type is std_logic_vector(3 downto 0);
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type dma_burst_length_array is array (natural range <>) of dma_burst_length_type;
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-- 64-bit data for DMA on AXI bus.
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subtype dma_data_type is std_logic_vector(63 downto 0);
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type dma_data_array is array(natural range <>) of dma_data_type;
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-- 14-bit ADC data.
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constant adc_data_bits: integer := 14;
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subtype adc_data_type is std_logic_vector(adc_data_bits - 1 downto 0);
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type adc_data_array is array(natural range <>) of adc_data_type;
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-- 24-bit averaged data.
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constant sample_data_bits: integer := 24;
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subtype sample_data_type is std_logic_vector(sample_data_bits - 1 downto 0);
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type sample_data_array is array(natural range <>) of sample_data_type;
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-- 48-bit timestamp.
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constant timestamp_bits: integer := 48;
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-- ADC input port type.
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type adc_data_input_type is array(0 to 1) of std_logic_vector(15 downto 0);
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-- Register addresses.
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constant reg_addr_mask: std_logic_vector(31 downto 0) := x"0010fffc";
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constant reg_info: natural := 16#000000#;
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constant reg_irq_enable: natural := 16#000010#;
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constant reg_irq_pending: natural := 16#000014#;
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constant reg_dma_en: natural := 16#000100#;
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constant reg_dma_status: natural := 16#000104#;
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constant reg_dma_clear: natural := 16#000108#;
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constant reg_timestamp_lo: natural := 16#000180#;
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constant reg_timestamp_hi: natural := 16#000184#;
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constant reg_timestamp_clear: natural := 16#000188#;
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constant reg_acq_addr_start: natural := 16#000200#;
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constant reg_acq_addr_end: natural := 16#000204#;
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constant reg_acq_addr_limit: natural := 16#000208#;
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constant reg_acq_addr_intr: natural := 16#00020c#;
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constant reg_acq_addr_ptr: natural := 16#000210#;
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constant reg_acq_dma_ctrl: natural := 16#000214#;
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constant reg_acq_intr_ctrl: natural := 16#000218#;
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constant reg_acq_dma_status: natural := 16#00021c#;
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constant reg_acquisition_en: natural := 16#000220#;
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constant reg_record_length: natural := 16#000224#;
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constant reg_decimation_factor: natural := 16#000228#;
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constant reg_shift_steps: natural := 16#00022c#;
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constant reg_averaging_en: natural := 16#000230#;
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constant reg_ch4_mode: natural := 16#000234#;
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constant reg_simulate_adc: natural := 16#000238#;
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constant reg_trigger_mode: natural := 16#000240#;
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constant reg_trigger_delay: natural := 16#000244#;
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constant reg_trigger_status: natural := 16#000248#;
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constant reg_adc_sample: natural := 16#000280#;
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constant reg_adc23_sample: natural := 16#000284#;
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constant reg_adc_range_clear: natural := 16#00028c#;
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constant reg_adc0_minmax: natural := 16#000290#;
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constant reg_adc1_minmax: natural := 16#000294#;
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constant reg_adc2_minmax: natural := 16#000298#;
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constant reg_adc3_minmax: natural := 16#00029c#;
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constant reg_tt_addr_start: natural := 16#000300#;
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constant reg_tt_addr_end: natural := 16#000304#;
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constant reg_tt_addr_limit: natural := 16#000308#;
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constant reg_tt_addr_intr: natural := 16#00030c#;
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constant reg_tt_addr_ptr: natural := 16#000310#;
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constant reg_tt_dma_ctrl: natural := 16#000314#;
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constant reg_tt_intr_ctrl: natural := 16#000318#;
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constant reg_tt_dma_status: natural := 16#00031c#;
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constant reg_timetagger_en: natural := 16#000320#;
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constant reg_timetagger_mark: natural := 16#000324#;
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constant reg_dig_simulate: natural := 16#000330#;
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constant reg_dig_sample: natural := 16#000338#;
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constant reg_led_state: natural := 16#000404#;
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constant reg_dma_buf_addr: natural := 16#100000#;
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constant reg_dma_buf_size: natural := 16#100004#;
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-- Firmware info word.
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constant fw_api_version: natural := 1;
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constant fw_version_major: natural := 0;
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constant fw_version_minor: natural := 6;
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constant fw_info_word: std_logic_vector(31 downto 0) :=
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x"4a"
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& std_logic_vector(to_unsigned(fw_api_version, 8))
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& std_logic_vector(to_unsigned(fw_version_major, 8))
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& std_logic_vector(to_unsigned(fw_version_minor, 8));
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-- Data stream.
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constant msg_adc_data: std_logic_vector(7 downto 0) := x"10";
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constant msg_trigger: std_logic_vector(7 downto 0) := x"11";
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constant msg_timetagger_data: std_logic_vector(7 downto 4) := x"2";
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constant msg_marker: std_logic_vector(7 downto 0) := x"30";
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constant msg_overflow: std_logic_vector(7 downto 0) := x"40";
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-- Control registers: read/write access by processor, output signals to FPGA.
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type registers_control is record
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irq_enable: std_logic;
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dma_en: std_logic;
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dma_clear: std_logic; -- single cycle
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timestamp_clear: std_logic; -- single cycle
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acq_addr_start: std_logic_vector(31 downto 7);
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acq_addr_end: std_logic_vector(31 downto 7);
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acq_addr_limit: std_logic_vector(31 downto 7);
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acq_addr_intr: std_logic_vector(31 downto 3);
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acq_dma_en: std_logic;
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acq_dma_init: std_logic; -- single cycle
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acq_intr_en: std_logic;
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acq_intr_clear: std_logic; -- single cycle
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acquisition_en: std_logic;
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record_length: std_logic_vector(15 downto 0);
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decimation_factor: std_logic_vector(17 downto 0);
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shift_steps: std_logic_vector(3 downto 0);
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averaging_en: std_logic;
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ch4_mode: std_logic;
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simulate_adc: std_logic;
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trig_auto_en: std_logic;
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trig_ext_en: std_logic;
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trig_force: std_logic; -- single cycle
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trig_ext_select: std_logic_vector(1 downto 0);
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trig_ext_falling: std_logic;
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trigger_delay: std_logic_vector(15 downto 0);
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adc_range_clear: std_logic;
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tt_addr_start: std_logic_vector(31 downto 7);
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tt_addr_end: std_logic_vector(31 downto 7);
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tt_addr_limit: std_logic_vector(31 downto 7);
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tt_addr_intr: std_logic_vector(31 downto 3);
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tt_dma_en: std_logic;
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tt_dma_init: std_logic; -- single cycle
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tt_intr_en: std_logic;
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tt_intr_clear: std_logic; -- single cycle
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timetagger_en: std_logic_vector(7 downto 0);
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timetagger_mark: std_logic; -- single cycle
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dig_simulate: std_logic;
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dig_sim_state: std_logic_vector(3 downto 0);
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led_state: std_logic_vector(7 downto 0);
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dma_buf_addr: std_logic_vector(31 downto 12);
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dma_buf_size: std_logic_vector(31 downto 12);
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end record;
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-- Status registers: input signals from FPGA, read-only access by processor.
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type registers_status is record
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irq_pending: std_logic_vector(1 downto 0);
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dma_busy: std_logic;
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dma_err_read: std_logic;
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dma_err_write: std_logic;
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dma_err_address: std_logic;
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dma_err_any: std_logic;
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timestamp: std_logic_vector(timestamp_bits - 1 downto 0);
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acq_addr_ptr: std_logic_vector(31 downto 3);
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acq_dma_busy: std_logic;
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trig_waiting: std_logic;
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adc_sample: adc_data_array(0 to 3);
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adc_min_value: adc_data_array(0 to 3);
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adc_max_value: adc_data_array(0 to 3);
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tt_addr_ptr: std_logic_vector(31 downto 3);
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tt_dma_busy: std_logic;
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dig_sample: std_logic_vector(3 downto 0);
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end record;
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constant registers_control_init: registers_control := (
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irq_enable => '0',
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dma_en => '0',
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dma_clear => '0',
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timestamp_clear => '0',
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acq_addr_start => (others => '0'),
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acq_addr_end => (others => '0'),
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acq_addr_limit => (others => '0'),
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acq_addr_intr => (others => '0'),
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acq_dma_en => '0',
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acq_dma_init => '0',
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acq_intr_en => '0',
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acq_intr_clear => '0',
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acquisition_en => '0',
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record_length => (others => '0'),
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decimation_factor => (others => '0'),
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shift_steps => (others => '0'),
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averaging_en => '0',
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ch4_mode => '0',
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simulate_adc => '0',
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trig_auto_en => '0',
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trig_ext_en => '0',
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trig_force => '0',
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trig_ext_select => (others => '0'),
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trig_ext_falling => '0',
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trigger_delay => (others => '0'),
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adc_range_clear => '0',
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tt_addr_start => (others => '0'),
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tt_addr_end => (others => '0'),
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tt_addr_limit => (others => '0'),
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tt_addr_intr => (others => '0'),
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tt_dma_en => '0',
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tt_dma_init => '0',
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tt_intr_en => '0',
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tt_intr_clear => '0',
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timetagger_en => (others => '0'),
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timetagger_mark => '0',
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dig_simulate => '0',
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dig_sim_state => (others => '0'),
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led_state => (others => '0'),
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dma_buf_addr => (others => '0'),
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dma_buf_size => (others => '0')
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);
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end package;
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