--
--  Generate timestamps.
--
--  Joris van Rantwijk 2024
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.puzzlefw_pkg.all;


entity timestamp_gen is

    port (
        -- Main clock, active on rising edge.
        clk:                in  std_logic;

        -- Reset, active high, synchronous to main clock.
        reset:              in  std_logic;

        -- High to reset the timestamp counter to 0.
        clear:              in  std_logic;

        -- Timestamp.
        timestamp:          out std_logic_vector(timestamp_bits - 1 downto 0)
    );

end entity;

architecture arch of timestamp_gen is

    signal r_counter: unsigned(timestamp_bits - 1 downto 0);

begin

    -- Drive output.
    timestamp <= std_logic_vector(r_counter);

    --
    -- Synchronous process.
    --
    process (clk) is
    begin
        if rising_edge(clk) then

            if (reset = '1') or (clear = '1') then
                r_counter <= (others => '0');
            else
                r_counter <= r_counter + 1;
            end if;

        end if;
    end process;

end architecture;