-- -- Global definitions for Red Pitaya PuzzleFW firmware. -- -- Joris van Rantwijk 2024 -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package puzzlefw_pkg is -- 32-bit address for DMA on AXI bus, aligned to 8-byte multiple. subtype dma_address_type is std_logic_vector(31 downto 3); type dma_address_array is array(natural range <>) of dma_address_type; -- Burst length for DMA on AXI bus as number of beats minus 1. subtype dma_burst_length_type is std_logic_vector(3 downto 0); type dma_burst_length_array is array (natural range <>) of dma_burst_length_type; -- 64-bit data for DMA on AXI bus. subtype dma_data_type is std_logic_vector(63 downto 0); type dma_data_array is array(natural range <>) of dma_data_type; -- 14-bit ADC data. constant adc_data_bits: integer := 14; subtype adc_data_type is std_logic_vector(adc_data_bits - 1 downto 0); type adc_data_array is array(natural range <>) of adc_data_type; -- 24-bit averaged data. constant sample_data_bits: integer := 24; subtype sample_data_type is std_logic_vector(sample_data_bits - 1 downto 0); type sample_data_array is array(natural range <>) of sample_data_type; -- 48-bit timestamp. constant timestamp_bits: integer := 48; -- ADC input port type. type adc_data_input_type is array(0 to 1) of std_logic_vector(15 downto 0); -- Register addresses. constant reg_addr_mask: std_logic_vector(31 downto 0) := x"0010fffc"; constant reg_info: natural := 16#000000#; constant reg_irq_enable: natural := 16#000010#; constant reg_irq_pending: natural := 16#000014#; constant reg_dma_en: natural := 16#000100#; constant reg_dma_status: natural := 16#000104#; constant reg_dma_clear: natural := 16#000108#; constant reg_timestamp_lo: natural := 16#000180#; constant reg_timestamp_hi: natural := 16#000184#; constant reg_timestamp_clear: natural := 16#000188#; constant reg_acq_addr_start: natural := 16#000200#; constant reg_acq_addr_end: natural := 16#000204#; constant reg_acq_addr_limit: natural := 16#000208#; constant reg_acq_addr_intr: natural := 16#00020c#; constant reg_acq_addr_ptr: natural := 16#000210#; constant reg_acq_channel_ctrl: natural := 16#000214#; constant reg_acq_intr_ctrl: natural := 16#000218#; constant reg_acquisition_en: natural := 16#000220#; constant reg_record_length: natural := 16#000224#; constant reg_decimation_factor: natural := 16#000228#; constant reg_shift_steps: natural := 16#00022c#; constant reg_averaging_en: natural := 16#000230#; constant reg_ch4_mode: natural := 16#000234#; constant reg_simulate_adc: natural := 16#000238#; constant reg_trigger_mode: natural := 16#000240#; constant reg_trigger_delay: natural := 16#000244#; constant reg_trigger_status: natural := 16#000248#; constant reg_test_led: natural := 16#000404#; constant reg_test_divider: natural := 16#000408#; constant reg_dma_buf_addr: natural := 16#100000#; constant reg_dma_buf_size: natural := 16#100004#; -- Firmware info word. constant fw_api_version: natural := 1; constant fw_version_major: natural := 0; constant fw_version_minor: natural := 3; constant fw_info_word: std_logic_vector(31 downto 0) := x"4a" & std_logic_vector(to_unsigned(fw_api_version, 8)) & std_logic_vector(to_unsigned(fw_version_major, 8)) & std_logic_vector(to_unsigned(fw_version_minor, 8)); -- Data stream. constant msg_adc_data: std_logic_vector(7 downto 0) := x"01"; constant msg_trigger: std_logic_vector(7 downto 0) := x"02"; constant msg_overflow: std_logic_vector(7 downto 0) := x"10"; -- Control registers: read/write access by processor, output signals to FPGA. type registers_control is record irq_enable: std_logic; test_led: std_logic_vector(7 downto 0); test_divider: std_logic_vector(15 downto 0); dma_en: std_logic; dma_clear: std_logic; -- single cycle timestamp_clear: std_logic; -- single cycle acq_addr_start: std_logic_vector(31 downto 7); acq_addr_end: std_logic_vector(31 downto 7); acq_addr_limit: std_logic_vector(31 downto 7); acq_addr_intr: std_logic_vector(31 downto 3); acq_channel_en: std_logic; acq_channel_init: std_logic; -- single cycle acq_intr_en: std_logic; acq_intr_clear: std_logic; -- single cycle acquisition_en: std_logic; record_length: std_logic_vector(15 downto 0); decimation_factor: std_logic_vector(17 downto 0); shift_steps: std_logic_vector(3 downto 0); averaging_en: std_logic; ch4_mode: std_logic; simulate_adc: std_logic; trig_auto_en: std_logic; trig_ext_en: std_logic; trig_force: std_logic; -- single cycle trig_ext_select: std_logic_vector(1 downto 0); trig_ext_falling: std_logic; trigger_delay: std_logic_vector(15 downto 0); dma_buf_addr: std_logic_vector(31 downto 12); dma_buf_size: std_logic_vector(31 downto 12); end record; -- Status registers: input signals from FPGA, read-only access by processor. type registers_status is record irq_pending: std_logic_vector(0 downto 0); dma_busy: std_logic; dma_err_read: std_logic; dma_err_write: std_logic; dma_err_address: std_logic; dma_err_any: std_logic; timestamp: std_logic_vector(timestamp_bits - 1 downto 0); acq_addr_ptr: std_logic_vector(31 downto 3); acq_channel_busy: std_logic; trig_waiting: std_logic; end record; constant registers_control_init: registers_control := ( irq_enable => '0', test_led => (others => '0'), test_divider => (others => '0'), dma_en => '0', dma_clear => '0', timestamp_clear => '0', acq_addr_start => (others => '0'), acq_addr_end => (others => '0'), acq_addr_limit => (others => '0'), acq_addr_intr => (others => '0'), acq_channel_en => '0', acq_channel_init => '0', acq_intr_en => '0', acq_intr_clear => '0', acquisition_en => '0', record_length => (others => '0'), decimation_factor => (others => '0'), shift_steps => (others => '0'), averaging_en => '0', ch4_mode => '0', simulate_adc => '0', trig_auto_en => '0', trig_ext_en => '0', trig_force => '0', trig_ext_select => (others => '0'), trig_ext_falling => '0', trigger_delay => (others => '0'), dma_buf_addr => (others => '0'), dma_buf_size => (others => '0') ); end package;