--
--  Manage the ADC sample stream.
--
--  Optionally generates simulated samples in place of real ADC data.
--  The simulated sample stream works as follows:
--   - Both simulated channels output a simple increasing ramp.
--   - The output of channel 0 increments at a rate of 1 per clock cycle.
--   - The output of channel 1 increments by 1 whenever channel 0 wraps around.
--
--  This entity adds 1 clock cycle delay in the ADC sample stream.
--
--  Joris van Rantwijk 2024
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.puzzlefw_pkg.all;


entity adc_sample_stream is

    port (
        -- Main clock, active on rising edge.
        clk:                in  std_logic;

        -- Reset, active high, synchronous to main clock.
        reset:              in  std_logic;

        -- High to select simulated samples in place of ADC data.
        simulate:           in  std_logic;

        -- Input sample stream from ADC.
        in_data:            in  adc_data_array(0 to 1);

        -- Output sample stream.
        out_data:           out adc_data_array(0 to 1)
    );

end entity;

architecture arch of adc_sample_stream is

    signal r_counter:   unsigned(2 * adc_data_bits - 1 downto 0);
    signal r_out_data:  adc_data_array(0 to 1);

begin

    -- Drive output ports.
    out_data <= r_out_data;

    --
    -- Synchronous process.
    --
    process (clk) is
    begin
        if rising_edge(clk) then

            -- Select ADC sample or simulated sample.
            if simulate = '1' then
                -- Output simulated sample.
                r_out_data(0) <= std_logic_vector(r_counter(adc_data_bits - 1 downto 0));
                r_out_data(1) <= std_logic_vector(r_counter(2 * adc_data_bits - 1 downto adc_data_bits));
            else
                -- Output real ADC sample.
                r_out_data <= in_data;
            end if;

            -- Update simulated sample stream.
            if reset = '1' then
                r_counter <= (others => '0');
            else
                r_counter <= r_counter + 1;
            end if;

        end if;
    end process;

end architecture;