--
--  Capture ADC sample data from FPGA input ports.
--
--  Input signals are captured on the rising edge of CLK.
--  This entity adds 2 clock cycles delay.
--
--  Joris van Rantwijk 2024
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.puzzlefw_pkg.all;


entity adc_capture is

    port (
        -- Main clock, active on rising edge.
        clk:                in  std_logic;

        -- Input signals.
        in_data:            in  std_logic_vector(adc_data_bits - 1 downto 0);

        -- Output sample stream.
        -- Produces one new ADC sample per clock cycle.
        out_data:           out adc_data_type
    );

end entity;

architecture arch of adc_capture is

    signal r_stage1:    std_logic_vector(adc_data_bits - 1 downto 0);
    signal r_stage2:    std_logic_vector(adc_data_bits - 1 downto 0);

begin

    -- Drive output ports.
    out_data <= r_stage2;

    --
    -- Synchronous process.
    --
    process (clk) is
    begin
        if rising_edge(clk) then

            -- Capture input signals into registers.
            -- These registers will be placed in IO flipflops through IOB constraints.
            r_stage1 <= in_data;

            -- Second register stage.
            -- These can be placed anywhere in the FPGA to optimize timing.
            r_stage2 <= r_stage1;

        end if;
    end process;

end architecture;