diff --git a/doc/devel_manual.md b/doc/devel_manual.md
index 3da2727..32a05fe 100644
--- a/doc/devel_manual.md
+++ b/doc/devel_manual.md
@@ -40,7 +40,7 @@ The following interfaces are used between the PS (ARM) and PL (FPGA):
   Used by embedded software to read and write registers in the FPGA via AXI and APB bus.
   This interface is mapped to addresses 0x43000000 to 0x431fffff in the PS address map.
 - S\_AXI\_HP0 <br>
-  Used by FPGA firmware to read and write to DDR memory.
+  Used by FPGA firmware to read and write DDR memory.
 - GPIO <br>
   The PS controls a few specific digital signals in the FPGA via GPIO lines.
   One of these lines is a global reset signal for the FPGA firmware.
@@ -56,25 +56,25 @@ The following interfaces are used between the PS (ARM) and PL (FPGA):
 ### ADC input timing
 
 The ADC transfers samples via a parallel source-synchronous interface.
-A 125 MHz clock is sent along with the samples.
+The interface is synchronous to a 125 MHz clock output signal from the ADC.
 This is also the main clock source of the FPGA design.
 
 On 2-input Red Pitaya boards, the ADC is hardwired to operate in _full rate CMOS mode_.
 Each analog channel has 14 parallel data signals from ADC to FPGA.
-These data signals transition on the falling clock edge, such that the FPGA can capture on the rising clock edge.
-The FPGA buffers the 125 MHz ADC clock through a PLL.
-Data signals are captured in the FPGA in IOB flip-flops, clocked on the rising edge of the buffered 125 MHz clock.
+These data signals transition on the falling clock edge and are captured by the FPGA on the rising clock edge.
+Data signals are captured in the FPGA in IOB flip-flops.
+These flip-flops are clocked on a 125 MHz clock, derived by a PLL from the ADC output clock.
 It turns out that a phase shift of 90 degrees in the PLL provides near-optimal timing for capturing the data signals.
 This follows from synthesizer timing reports and has been confirmed experimentally by testing different PLL phase shift settings.
 
 On 4-input Red Pitaya boards, only 7 parallel data signals per analog channel are connected from the ADCs to the FPGA.
 The ADCs must be programmed (via SPI) to operate in _double data rate CMOS mode_.
-In this mode, the ADC still outputs a 125 MHz clock, but data lines transition on both edges of the clock.
+In this mode, the data lines transition on both edges of the 125 MHz clock.
 The data signals are routed through IDELAY components in the FPGA before being captured in IDDR registers.
 The IDDR are clocked on the 125 MHz clock from the ADC that produces the samples (without PLL).
 The IDELAY components use a fixed delay, tuned to 2.34 ns to optimize data capture timing.
 Timing reports indicate that this provides sufficient margin.
-This has been confirmed experimentally by phase-shifting the ADC output clock.
+This has been confirmed experimentally by testing different phase-shift settings of the ADC output clock.
 The main FPGA design runs on a 125 MHz clock, derived by a PLL from the ADC that samples channels 1 and 2.
 Transferring samples from channels 3 and 4 to the main clock is slightly tricky because the two ADC clocks may be skewed with respect to each other.
 A few mysterious timing constraints were added to deal with this.
@@ -82,7 +82,7 @@ A few mysterious timing constraints were added to deal with this.
 
 ## Embedded software overview
 
-The purpose of the embedded software is to make the system remote accessible via the network.
+The purpose of the embedded software is to make the system remotely accessible via the network.
 The software collects data from the FPGA and transmits it via TCP.
 Similarly, the software accepts remote control commands via TCP and executes these by accessing registers in the FPGA.
 
@@ -167,11 +167,11 @@ The kernel module itself has minimal functionality.
 Its only functions are:
 
  - mapping the register address range of the FPGA to user space via mmap
- - mapping the DMA buffer in DDR RAM to user space via mmap
+ - mapping the DMA buffer to user space via mmap
  - handling FPGA interrupts and notifying user space via UIO
 
 All non-trivial interactions with the FPGA are done in user space.
-This includes managing the data flow via DMA.
+This includes managing the DMA data flow.
 
 ### User space software
 
@@ -199,8 +199,8 @@ The following files are stored there:
 
 The configuration partition is temporarily mounted read-only during boot, to read the configuration files.
 Otherwise, the partition is only accessed when the configuration is modified.
-In that case, the partition is temporarily mounted to write the updated files, then unmounted again.
-As a result, writes to the SD card occur only when the user applies a change in the persistent configuration of the system.
+In such cases, the partition is temporarily mounted to write the updated files, then unmounted again.
+As a result, writes to the SD card occur only when the user changes the persistent configuration of the system.
 This avoids unnecessary wear of the SD card.
 
 
@@ -454,7 +454,7 @@ An easier way to set up the SD card is by building an image file and writing it
 The SD card contains two partitions:
 
 - `/dev/mmcblk0p1` is a 256 MB partition with FAT filesystem
-- `/dev/mmcblk0p2` is a 256 MB partition with an EXT4 filesystem
+- `/dev/mmcblk0p2` is a 256 MB partition with an Ext4 filesystem
 
 The FAT partition contains the following files:
 
@@ -469,7 +469,7 @@ The FAT partition contains the following files:
 | `puzzlefw_top.bit.bin`     | FPGA firmware image for 2-input board |
 | `puzzlefw_top_4ch.bit.bin` | FPGA firmware image for 4-input board |
 
-The EXT4 partition can be left empty initially.
+The Ext4 partition can be left empty initially.
 Configuration files will be written to this partition by the embedded system.
 
 The following commands may be used to format the two partitions:
diff --git a/doc/fpga_block_design.png b/doc/fpga_block_design.png
index b978453..2afe01b 100644
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