From 5ceb5ad8820a2d48fc80d1c93a38a9c413db14ae Mon Sep 17 00:00:00 2001
From: Joris van Rantwijk <joris@jorisvr.nl>
Date: Sun, 22 Sep 2024 15:01:25 +0200
Subject: [PATCH] Delay timetagger signal to match ADC trigger

---
 fpga/rtl/puzzlefw_pkg.vhd |  2 +-
 fpga/rtl/timetagger.vhd   | 28 ++++++++++++++++++++--------
 2 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/fpga/rtl/puzzlefw_pkg.vhd b/fpga/rtl/puzzlefw_pkg.vhd
index 541f1d0..3c29828 100644
--- a/fpga/rtl/puzzlefw_pkg.vhd
+++ b/fpga/rtl/puzzlefw_pkg.vhd
@@ -94,7 +94,7 @@ package puzzlefw_pkg is
     -- Firmware info word.
     constant fw_api_version:        natural := 1;
     constant fw_version_major:      natural := 0;
-    constant fw_version_minor:      natural := 8;
+    constant fw_version_minor:      natural := 9;
     constant fw_info_word:          std_logic_vector(31 downto 0) :=
         x"4a"
         & std_logic_vector(to_unsigned(fw_api_version, 8))
diff --git a/fpga/rtl/timetagger.vhd b/fpga/rtl/timetagger.vhd
index c43a491..c0b14fa 100644
--- a/fpga/rtl/timetagger.vhd
+++ b/fpga/rtl/timetagger.vhd
@@ -64,7 +64,9 @@ architecture arch of timetagger is
         overflow:           std_logic;
         marker_pending:     std_logic;
         marker_holdoff:     std_logic;
+        cur_sample:         std_logic_vector(3 downto 0);
         prev_sample:        std_logic_vector(3 downto 0);
+        detected_events:    std_logic_vector(3 downto 0);
         pending_events:     std_logic_vector(3 downto 0);
         fifo_in_valid:      std_logic;
         fifo_in_evmask:     std_logic_vector(3 downto 0);
@@ -76,7 +78,9 @@ architecture arch of timetagger is
         overflow            => '0',
         marker_pending      => '0',
         marker_holdoff      => '0',
+        cur_sample          => (others => '0'),
         prev_sample         => (others => '0'),
+        detected_events     => (others => '0'),
         pending_events      => (others => '0'),
         fifo_in_valid       => '0',
         fifo_in_evmask      => (others => '0'),
@@ -184,20 +188,28 @@ begin
 
         --
         -- Detect events and write to FIFO.
-        ---
+        --
+        -- This logic delays the digital input path in order to match the delay
+        -- in the analog acquisition chain. An event timestamp is assigned
+        -- after a delay of 3 clock cycles following a change in "dig_sample".
+        -- 
 
-        -- Hold previous input state.
-        v.prev_sample := dig_sample;
+        -- Capture input state.
+        v.cur_sample := dig_sample;
+
+        -- Keep previous input state.
+        v.prev_sample := r.cur_sample;
 
         -- Detect events on enabled channels.
         for i in 0 to 3 loop
-            v.fifo_in_evmask(i) :=
-                (channel_en(2*i) and (not r.prev_sample(i)) and dig_sample(i))
-                or (channel_en(2*i+1) and r.prev_sample(i) and (not dig_sample(i)));
+            v.detected_events(i) :=
+                (channel_en(2*i) and (not r.prev_sample(i)) and r.cur_sample(i))
+                or (channel_en(2*i+1) and r.prev_sample(i) and (not r.cur_sample(i)));
         end loop;
 
-        -- Write changes to FIFO.
-        if (r.overflow = '0') and (or_reduce(v.fifo_in_evmask) = '1') then
+        -- Write detected events to FIFO.
+        v.fifo_in_evmask := r.detected_events;
+        if (r.overflow = '0') and (or_reduce(r.detected_events) = '1') then
             v.fifo_in_valid := '1';
         else
             v.fifo_in_valid := '0';