From 4d79fecfdc7a64064a5a5cf995df3740a47f4555 Mon Sep 17 00:00:00 2001
From: Joris van Rantwijk <joris@jorisvr.nl>
Date: Sun, 6 Oct 2024 12:58:11 +0200
Subject: [PATCH] Change FCLK0 frequency to 200 MHz

This clock is used as REFCLK for IODELAYCTRL in the 4-input design.
---
 .../sources_1/bd/puzzlefw/puzzlefw.bd         | 46 +++++++++----------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd b/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd
index 44478ad..f25bee3 100644
--- a/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd
+++ b/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd
@@ -1,7 +1,7 @@
 {
   "design": {
     "design_info": {
-      "boundary_crc": "0xFEDCCBE640F58A4D",
+      "boundary_crc": "0xFEDCCBE69F795227",
       "device": "xc7z010clg400-1",
       "gen_directory": "../../../../redpitaya_puzzlefw.gen/sources_1/bd/puzzlefw",
       "name": "puzzlefw",
@@ -269,7 +269,7 @@
             "value_src": "default_prop"
           },
           "FREQ_HZ": {
-            "value": "125000000",
+            "value": "200000000",
             "value_src": "user_prop"
           },
           "FREQ_TOLERANCE_HZ": {
@@ -358,7 +358,7 @@
             "value": "10.000000"
           },
           "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
-            "value": "125.000000"
+            "value": "200.000000"
           },
           "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
             "value": "10.000000"
@@ -412,7 +412,7 @@
             "value": "111.111115"
           },
           "PCW_CLK0_FREQ": {
-            "value": "125000000"
+            "value": "200000000"
           },
           "PCW_CLK1_FREQ": {
             "value": "10000000"
@@ -523,7 +523,7 @@
             "value": "IO PLL"
           },
           "PCW_FPGA0_PERIPHERAL_FREQMHZ": {
-            "value": "125"
+            "value": "200"
           },
           "PCW_FPGA1_PERIPHERAL_FREQMHZ": {
             "value": "250"
@@ -1503,17 +1503,17 @@
               }
             },
             "interface_nets": {
-              "s00_couplers_to_auto_pc": {
-                "interface_ports": [
-                  "S_AXI",
-                  "auto_pc/S_AXI"
-                ]
-              },
               "auto_pc_to_s00_couplers": {
                 "interface_ports": [
                   "M_AXI",
                   "auto_pc/M_AXI"
                 ]
+              },
+              "s00_couplers_to_auto_pc": {
+                "interface_ports": [
+                  "S_AXI",
+                  "auto_pc/S_AXI"
+                ]
               }
             },
             "nets": {
@@ -1609,18 +1609,24 @@
           "processing_system7_0/DDR"
         ]
       },
-      "S_AXI_HP0_0_1": {
-        "interface_ports": [
-          "S_AXI_HP0_0",
-          "processing_system7_0/S_AXI_HP0"
-        ]
-      },
       "axi_interconnect_0_M00_AXI": {
         "interface_ports": [
           "axi_interconnect_0/M00_AXI",
           "axi_apb_bridge_0/AXI4_LITE"
         ]
       },
+      "processing_system7_0_M_AXI_GP0": {
+        "interface_ports": [
+          "processing_system7_0/M_AXI_GP0",
+          "axi_interconnect_0/S00_AXI"
+        ]
+      },
+      "S_AXI_HP0_0_1": {
+        "interface_ports": [
+          "S_AXI_HP0_0",
+          "processing_system7_0/S_AXI_HP0"
+        ]
+      },
       "processing_system7_0_FIXED_IO": {
         "interface_ports": [
           "FIXED_IO_0",
@@ -1632,12 +1638,6 @@
           "APB_M_0",
           "axi_apb_bridge_0/APB_M"
         ]
-      },
-      "processing_system7_0_M_AXI_GP0": {
-        "interface_ports": [
-          "processing_system7_0/M_AXI_GP0",
-          "axi_interconnect_0/S00_AXI"
-        ]
       }
     },
     "nets": {