diff --git a/fpga/vivado/redpitaya_puzzlefw.xpr b/fpga/vivado/redpitaya_puzzlefw.xpr
index 6719bff..110fa0d 100644
--- a/fpga/vivado/redpitaya_puzzlefw.xpr
+++ b/fpga/vivado/redpitaya_puzzlefw.xpr
@@ -83,14 +83,14 @@
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
-        <CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_axi_apb_bridge_0_0/puzzlefw_axi_apb_bridge_0_0.xci">
-          <Proxy FileSetName="puzzlefw_axi_apb_bridge_0_0"/>
+        <CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_processing_system7_0_0/puzzlefw_processing_system7_0_0.xci">
+          <Proxy FileSetName="puzzlefw_processing_system7_0_0"/>
         </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_proc_sys_reset_0_0/puzzlefw_proc_sys_reset_0_0.xci">
           <Proxy FileSetName="puzzlefw_proc_sys_reset_0_0"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_processing_system7_0_0/puzzlefw_processing_system7_0_0.xci">
-          <Proxy FileSetName="puzzlefw_processing_system7_0_0"/>
+        <CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_axi_apb_bridge_0_0/puzzlefw_axi_apb_bridge_0_0.xci">
+          <Proxy FileSetName="puzzlefw_axi_apb_bridge_0_0"/>
         </CompFileExtendedInfo>
       </File>
       <File Path="$PGENDIR/sources_1/bd/puzzlefw/hdl/puzzlefw_wrapper.vhd">
@@ -159,6 +159,12 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/../rtl/deglitch.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/../rtl/dma_axi_master.vhd">
         <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -189,6 +195,18 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/../rtl/syncdff.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rtl/timetagger.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/../rtl/puzzlefw_top.vhd">
         <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -320,7 +338,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
         <Step Id="init_design"/>
@@ -333,6 +351,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>