diff --git a/fpga/rtl/puzzlefw_pkg.vhd b/fpga/rtl/puzzlefw_pkg.vhd
index c599fec..00f366b 100644
--- a/fpga/rtl/puzzlefw_pkg.vhd
+++ b/fpga/rtl/puzzlefw_pkg.vhd
@@ -94,7 +94,7 @@ package puzzlefw_pkg is
     -- Firmware info word.
     constant fw_api_version:        natural := 1;
     constant fw_version_major:      natural := 0;
-    constant fw_version_minor:      natural := 11;
+    constant fw_version_minor:      natural := 12;
     constant fw_info_word:          std_logic_vector(31 downto 0) :=
         x"4a"
         & std_logic_vector(to_unsigned(fw_api_version, 8))
diff --git a/fpga/rtl/puzzlefw_top.vhd b/fpga/rtl/puzzlefw_top.vhd
index 9ce4abc..d70d4b2 100644
--- a/fpga/rtl/puzzlefw_top.vhd
+++ b/fpga/rtl/puzzlefw_top.vhd
@@ -72,11 +72,11 @@ architecture arch of puzzlefw_top is
     signal clk_fclk:        std_logic;
 
     -- Reset signals.
-    signal s_gpio_reset_n:  std_logic;  -- reset signal from GPIO, active low
+    signal s_ext_reset_n:   std_logic;  -- reset signal from GPIO, active low
     signal s_pll_reset:     std_logic;  -- reset signal for PLL
     signal s_pll_locked:    std_logic;  -- PLL locked status
-    signal s_ext_reset_n:   std_logic;  -- reset signal for processing system
     signal s_reset:         std_logic;  -- main reset, synchronized to clk_adc
+    signal r_reset_done:    std_logic;  -- reset status report via GPIO
 
     -- Internal clock signals.
     signal s_adc_clk_ibuf:  std_logic;
@@ -181,7 +181,7 @@ begin
 
     -- Global FPGA reset.
     -- GPIO(0) = '0' to reset.
-    s_gpio_reset_n  <= s_gpio_out(0);
+    s_ext_reset_n   <= s_gpio_out(0);
 
     -- ADC clock duty cycle stabilizer.
     -- GPIO(2) = '1' to enable, '0' to disable.
@@ -189,7 +189,7 @@ begin
 
     -- GPIO inputs to the PS.
     -- GPIO(1) = '0' while in reset, '1' when reset released.
-    s_gpio_in(1) <= not s_reset;
+    s_gpio_in(1) <= r_reset_done;
     s_gpio_in(0) <= '0';
     s_gpio_in(23 downto 2) <= (others => '0');
 
@@ -247,10 +247,7 @@ begin
             CLKFBIN             => s_pll_clkfbin );
 
     -- Reset PLL when external reset is applied.
-    s_pll_reset <= not s_gpio_reset_n;
-
-    -- Reset processing system when PLL is not locked.
-    s_ext_reset_n <= s_gpio_reset_n and s_pll_locked;
+    s_pll_reset <= not s_ext_reset_n;
 
     -- Clock buffers for PLL.
     inst_bufg_pll_clkfb: BUFG
@@ -270,6 +267,7 @@ begin
             ps_fclk             => clk_fclk,
             peripheral_reset_0(0) => s_reset,
             ext_reset_in_0      => s_ext_reset_n,
+            dcm_locked_0        => s_pll_locked,
             DDR_0_addr          => DDR_0_addr,
             DDR_0_ba            => DDR_0_ba,
             DDR_0_cas_n         => DDR_0_cas_n,
@@ -643,11 +641,24 @@ begin
     s_irq_f2p(0) <= s_reg_control.irq_enable and or_reduce(s_irq_pending);
     s_irq_f2p(7 downto 1) <= (others => '0');
 
+    -- Report reset status via GPIO.
+    process (clk_adc, s_ext_reset_n) is
+    begin
+        if s_ext_reset_n = '0' then
+            r_reset_done <= '0';
+        elsif rising_edge(clk_adc) then
+            r_reset_done <= not s_reset;
+        end if;
+    end process;
+
     -- Blinking LED, 1 Hz.
     process (clk_adc) is
     begin
         if rising_edge(clk_adc) then
-            if r_adcclk_cnt = 62499999 then
+            if s_reset = '1' then
+                r_adcclk_cnt <= (others => '0');
+                r_adcclk_led <= '0';
+            elsif r_adcclk_cnt = 62499999 then
                 r_adcclk_cnt <= (others => '0');
                 r_adcclk_led <= not r_adcclk_led;
             else
diff --git a/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd b/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd
index 4366e8e..44478ad 100644
--- a/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd
+++ b/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd
@@ -1,7 +1,7 @@
 {
   "design": {
     "design_info": {
-      "boundary_crc": "0x9117A810100AEEF7",
+      "boundary_crc": "0xFEDCCBE640F58A4D",
       "device": "xc7z010clg400-1",
       "gen_directory": "../../../../redpitaya_puzzlefw.gen/sources_1/bd/puzzlefw",
       "name": "puzzlefw",
@@ -330,6 +330,9 @@
       },
       "SPI0_MOSI_T_0": {
         "direction": "O"
+      },
+      "dcm_locked_0": {
+        "direction": "I"
       }
     },
     "components": {
@@ -1747,6 +1750,12 @@
           "xlconstant_0/dout",
           "processing_system7_0/SPI0_SS_I"
         ]
+      },
+      "dcm_locked_0_1": {
+        "ports": [
+          "dcm_locked_0",
+          "proc_sys_reset_0/dcm_locked"
+        ]
       }
     },
     "addressing": {