diff --git a/fpga/rtl/puzzlefw_pkg.vhd b/fpga/rtl/puzzlefw_pkg.vhd index 91e8d50..5e3217c 100644 --- a/fpga/rtl/puzzlefw_pkg.vhd +++ b/fpga/rtl/puzzlefw_pkg.vhd @@ -55,8 +55,9 @@ package puzzlefw_pkg is constant reg_acq_addr_limit: natural := 16#000208#; constant reg_acq_addr_intr: natural := 16#00020c#; constant reg_acq_addr_ptr: natural := 16#000210#; - constant reg_acq_channel_ctrl: natural := 16#000214#; + constant reg_acq_dma_ctrl: natural := 16#000214#; constant reg_acq_intr_ctrl: natural := 16#000218#; + constant reg_acq_dma_status: natural := 16#00021c#; constant reg_acquisition_en: natural := 16#000220#; constant reg_record_length: natural := 16#000224#; constant reg_decimation_factor: natural := 16#000228#; @@ -106,8 +107,8 @@ package puzzlefw_pkg is acq_addr_end: std_logic_vector(31 downto 7); acq_addr_limit: std_logic_vector(31 downto 7); acq_addr_intr: std_logic_vector(31 downto 3); - acq_channel_en: std_logic; - acq_channel_init: std_logic; -- single cycle + acq_dma_en: std_logic; + acq_dma_init: std_logic; -- single cycle acq_intr_en: std_logic; acq_intr_clear: std_logic; -- single cycle acquisition_en: std_logic; @@ -138,7 +139,7 @@ package puzzlefw_pkg is dma_err_any: std_logic; timestamp: std_logic_vector(timestamp_bits - 1 downto 0); acq_addr_ptr: std_logic_vector(31 downto 3); - acq_channel_busy: std_logic; + acq_dma_busy: std_logic; trig_waiting: std_logic; adc_sample: adc_data_array(0 to 3); adc_min_value: adc_data_array(0 to 3); @@ -156,8 +157,8 @@ package puzzlefw_pkg is acq_addr_end => (others => '0'), acq_addr_limit => (others => '0'), acq_addr_intr => (others => '0'), - acq_channel_en => '0', - acq_channel_init => '0', + acq_dma_en => '0', + acq_dma_init => '0', acq_intr_en => '0', acq_intr_clear => '0', acquisition_en => '0', diff --git a/fpga/rtl/puzzlefw_top.vhd b/fpga/rtl/puzzlefw_top.vhd index 464c483..67ed76c 100644 --- a/fpga/rtl/puzzlefw_top.vhd +++ b/fpga/rtl/puzzlefw_top.vhd @@ -355,7 +355,7 @@ begin ); -- DMA Write Channel - inst_write_channel: entity work.dma_write_channel + inst_acq_dma: entity work.dma_write_channel generic map ( transfer_size_bits => 4, queue_size_bits => 10, @@ -363,9 +363,9 @@ begin port map ( clk => clk_adc, reset => s_reset, - channel_en => s_reg_control.acq_channel_en, - channel_busy => s_reg_status.acq_channel_busy, - channel_init => s_reg_control.acq_channel_init, + channel_en => s_reg_control.acq_dma_en, + channel_busy => s_reg_status.acq_dma_busy, + channel_init => s_reg_control.acq_dma_init, addr_start => s_reg_control.acq_addr_start, addr_end => s_reg_control.acq_addr_end, addr_limit => s_reg_control.acq_addr_limit, diff --git a/fpga/rtl/registers.vhd b/fpga/rtl/registers.vhd index ddb8b62..a8d3c70 100644 --- a/fpga/rtl/registers.vhd +++ b/fpga/rtl/registers.vhd @@ -72,7 +72,7 @@ begin -- Clear single-cycle trigger pulses. v.reg_control.dma_clear := '0'; v.reg_control.timestamp_clear := '0'; - v.reg_control.acq_channel_init := '0'; + v.reg_control.acq_dma_init := '0'; v.reg_control.acq_intr_clear := '0'; v.reg_control.trig_force := '0'; v.reg_control.adc_range_clear := '0'; @@ -105,10 +105,10 @@ begin when reg_acq_addr_limit => v.prdata(31 downto 7) := r.reg_control.acq_addr_limit; when reg_acq_addr_intr => v.prdata(31 downto 3) := r.reg_control.acq_addr_intr; when reg_acq_addr_ptr => v.prdata(31 downto 3) := reg_status.acq_addr_ptr; - when reg_acq_channel_ctrl => - v.prdata(0) := r.reg_control.acq_channel_en; - v.prdata(8) := reg_status.acq_channel_busy; + when reg_acq_dma_ctrl => + v.prdata(0) := r.reg_control.acq_dma_en; when reg_acq_intr_ctrl => v.prdata(0) := r.reg_control.acq_intr_en; + when reg_acq_dma_status => v.prdata(0) := reg_status.acq_dma_busy; when reg_acquisition_en => v.prdata(0) := r.reg_control.acquisition_en; when reg_record_length => v.prdata(15 downto 0) := r.reg_control.record_length; when reg_decimation_factor => v.prdata(17 downto 0) := r.reg_control.decimation_factor; @@ -161,9 +161,9 @@ begin when reg_acq_addr_end => v.reg_control.acq_addr_end := apb_pwdata(31 downto 7); when reg_acq_addr_limit => v.reg_control.acq_addr_limit := apb_pwdata(31 downto 7); when reg_acq_addr_intr => v.reg_control.acq_addr_intr := apb_pwdata(31 downto 3); - when reg_acq_channel_ctrl => - v.reg_control.acq_channel_en := apb_pwdata(0); - v.reg_control.acq_channel_init := apb_pwdata(1); + when reg_acq_dma_ctrl => + v.reg_control.acq_dma_en := apb_pwdata(0); + v.reg_control.acq_dma_init := apb_pwdata(1); when reg_acq_intr_ctrl => v.reg_control.acq_intr_en := apb_pwdata(0); v.reg_control.acq_intr_clear := apb_pwdata(1); diff --git a/os/src/userspace/testje.c b/os/src/userspace/testje.c index 32d67bd..f686c0a 100644 --- a/os/src/userspace/testje.c +++ b/os/src/userspace/testje.c @@ -39,8 +39,9 @@ #define REG_ACQ_ADDR_LIMIT 0x0208 #define REG_ACQ_ADDR_INTR 0x020c #define REG_ACQ_ADDR_PTR 0x0210 -#define REG_ACQ_CHANNEL_CTRL 0x0214 +#define REG_ACQ_DMA_CTRL 0x0214 #define REG_ACQ_INTR_CTRL 0x0218 +#define REG_ACQ_DMA_STATUS 0x021c #define REG_ACQUISITION_EN 0x0220 #define REG_RECORD_LENGTH 0x0224 #define REG_DECIMATION_FACTOR 0x0228 @@ -575,12 +576,18 @@ static void show_status(struct puzzlefw_context *ctx) v = puzzlefw_read_reg(ctx, REG_ACQ_ADDR_PTR); printf(" acq_addr_ptr = 0x%08x\n", v); - v = puzzlefw_read_reg(ctx, REG_ACQ_CHANNEL_CTRL); - printf(" acq_channel_ctrl = 0x%08x\n", v); + v = puzzlefw_read_reg(ctx, REG_ACQ_DMA_CTRL); + printf(" acq_dma_ctrl = 0x%08x\n", v); + + v = puzzlefw_read_reg(ctx, REG_ACQ_DMA_STATUS); + printf(" acq_dma_status = 0x%08x\n", v); v = puzzlefw_read_reg(ctx, REG_ACQ_INTR_CTRL); printf(" acq_intr_ctrl = 0x%08x\n", v); + v = puzzlefw_read_reg(ctx, REG_ACQUISITION_EN); + printf(" acquisition_en = 0x%08x\n", v); + v = puzzlefw_read_reg(ctx, REG_SIMULATE_ADC); printf(" simulate_adc = 0x%08x\n", v); @@ -672,7 +679,7 @@ static void blast_dma(struct puzzlefw_context *ctx) printf("Starting DMA blaster ...\n"); // Disable DMA writer. - puzzlefw_write_reg(ctx, REG_ACQ_CHANNEL_CTRL, 0); + puzzlefw_write_reg(ctx, REG_ACQ_DMA_CTRL, 0); // Setup DMA buffer. puzzlefw_write_reg(ctx, REG_ACQ_ADDR_START, 0); @@ -682,10 +689,10 @@ static void blast_dma(struct puzzlefw_context *ctx) puzzlefw_write_reg(ctx, REG_ACQ_ADDR_LIMIT, 0xffffffff); // Initialize DMA writer. - puzzlefw_write_reg(ctx, REG_ACQ_CHANNEL_CTRL, 2); + puzzlefw_write_reg(ctx, REG_ACQ_DMA_CTRL, 2); // Enable DMA writer. - puzzlefw_write_reg(ctx, REG_ACQ_CHANNEL_CTRL, 1); + puzzlefw_write_reg(ctx, REG_ACQ_DMA_CTRL, 1); struct timespec tp; tp.tv_sec = 10; @@ -693,7 +700,7 @@ static void blast_dma(struct puzzlefw_context *ctx) clock_nanosleep(CLOCK_MONOTONIC, 0, &tp, NULL); // Disable DMA writer. - puzzlefw_write_reg(ctx, REG_ACQ_CHANNEL_CTRL, 0); + puzzlefw_write_reg(ctx, REG_ACQ_DMA_CTRL, 0); printf("Stopped DMA blaster\n"); } @@ -856,7 +863,7 @@ int transmit_dma_data(struct puzzlefw_context *ctx, int conn) puzzlefw_write_reg(ctx, REG_DMA_EN, 0); // Disable DMA write channel. - puzzlefw_write_reg(ctx, REG_ACQ_CHANNEL_CTRL, 0); + puzzlefw_write_reg(ctx, REG_ACQ_DMA_CTRL, 0); // Initialize DMA write buffer. puzzlefw_write_reg(ctx, REG_ACQ_ADDR_START, 0); @@ -874,10 +881,10 @@ int transmit_dma_data(struct puzzlefw_context *ctx, int conn) puzzlefw_write_reg(ctx, REG_DMA_EN, 1); // Initialize DMA writer. - puzzlefw_write_reg(ctx, REG_ACQ_CHANNEL_CTRL, 2); + puzzlefw_write_reg(ctx, REG_ACQ_DMA_CTRL, 2); // Enable DMA writer. - puzzlefw_write_reg(ctx, REG_ACQ_CHANNEL_CTRL, 1); + puzzlefw_write_reg(ctx, REG_ACQ_DMA_CTRL, 1); uint32_t read_pointer = 0; int ret; @@ -971,7 +978,7 @@ int transmit_dma_data(struct puzzlefw_context *ctx, int conn) puzzlefw_write_reg(ctx, REG_DMA_EN, 0); // Disable DMA write channel. - puzzlefw_write_reg(ctx, REG_ACQ_CHANNEL_CTRL, 0); + puzzlefw_write_reg(ctx, REG_ACQ_DMA_CTRL, 0); // Disable DMA writer interrupts; clear interrupt status. puzzlefw_write_reg(ctx, REG_ACQ_INTR_CTRL, 2);