From 33db3d5231f347792535365055f13b78aec5f097 Mon Sep 17 00:00:00 2001
From: Joris van Rantwijk <joris@jorisvr.nl>
Date: Tue, 8 Oct 2024 16:48:11 +0200
Subject: [PATCH] Remove board name from FPGA build script

---
 fpga/vivado/nonproject.tcl | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/fpga/vivado/nonproject.tcl b/fpga/vivado/nonproject.tcl
index 6922a57..a86dd4b 100644
--- a/fpga/vivado/nonproject.tcl
+++ b/fpga/vivado/nonproject.tcl
@@ -9,12 +9,12 @@
 # This is used by "synth_design".
 set_part xc7z010clg400-1
 
-# Specify path to RedPitaya board definition.
-set_param board.repoPaths [list "RedPitaya-FPGA/brd"]
+## Specify path to RedPitaya board definition.
+#set_param board.repoPaths [list "RedPitaya-FPGA/brd"]
 
-# Specify board type.
-# Unclear whether this is required.
-set_property board_part redpitaya.com:redpitaya:part0:1.1 [current_project]
+## Specify board type.
+## Unclear whether this is required.
+#set_property board_part redpitaya.com:redpitaya:part0:1.1 [current_project]
 
 # Specify HDL language.
 # This determines the language of the HDL wrapper for the block design.