From 2c23fa705d452d71e0dc505c718163fb061010f9 Mon Sep 17 00:00:00 2001
From: Joris van Rantwijk <joris@jorisvr.nl>
Date: Sun, 7 Jan 2024 00:52:36 +0100
Subject: [PATCH] Add devicetree (work in progress)

---
 os/14_build_devicetree.sh            |  16 +++
 os/devicetree/redpitaya_puzzlefw.dts | 208 +++++++++++++++++++++++++++
 2 files changed, 224 insertions(+)
 create mode 100755 os/14_build_devicetree.sh
 create mode 100644 os/devicetree/redpitaya_puzzlefw.dts

diff --git a/os/14_build_devicetree.sh b/os/14_build_devicetree.sh
new file mode 100755
index 0000000..cf063f8
--- /dev/null
+++ b/os/14_build_devicetree.sh
@@ -0,0 +1,16 @@
+#!/bin/bash
+
+set -e
+
+. script_env
+
+DTC="$LINUX_DIR/scripts/dtc/dtc"
+
+if [ ! -x "$DTC" ]; then
+    echo "ERROR: Missing $DTC" >&2
+    echo "       Build Linux kernel to build the device tree compiler" >&2
+    exit 1
+fi
+
+$DTC --symbols -I dts -O dtb -i "$LINUX_DIR/arch/arm/boot/dts/xilinx" -o devicetree/devicetree.dtb devicetree/redpitaya_puzzlefw.dts
+
diff --git a/os/devicetree/redpitaya_puzzlefw.dts b/os/devicetree/redpitaya_puzzlefw.dts
new file mode 100644
index 0000000..3c9bfff
--- /dev/null
+++ b/os/devicetree/redpitaya_puzzlefw.dts
@@ -0,0 +1,208 @@
+/*
+ * Device tree for Red Pitaya PuzzleFw firmware.
+ */
+
+/dts-v1/;
+
+// Include defaults from Linux kernel source tree.
+/include/ "zynq-7000.dtsi"
+
+/ {
+	model = "RedPitaya PuzzleFW";
+	compatible = "xlnx,zynq-7000";
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		ethernet0 = &gem0;
+		i2c0 = &i2c0;
+		serial0 = &uart0;
+		mmc0 = &sdhci0;
+	};
+
+	// Red Pitaya: 512 MByte DDR RAM at address 0x00000000
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x20000000>;
+	};
+
+	// Red Pitaya: 2 LEDs controlled by PS
+	gpio-leds {
+		compatible = "gpio-leds";
+		led-8-yellow {
+			label = "led8";
+			gpios = <&gpio0 0 0>;
+			default-state = "off";
+			linux,default-trigger = "mmc0";
+		};
+		led-9-red {
+			label = "led9";
+			gpios = <&gpio0 7 0>;
+			default-state = "off";
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+
+	// Register range and interrupts for FPGA logic
+	puzzlefw@43c00000 {
+		compatible = "jigsaw,puzzlefw";
+		//
+		// Register address mapping:
+		//
+		// Address 0x43000000 .. 0x430fffff (1 MB) = user registers
+		// Address 0x43100000 .. 0x43100fff (4 kB) = setup registers
+		//
+		reg = <0x43000000 0x100000>,
+		      <0x43100000 0x1000>;
+		//
+		// The FPGA firmware uses interrupts
+		//   IRQ_F2P[0] .. IRQ_F2P[3]
+		//
+		// These correspond to IRQ 61 .. 64 in the GIC.
+		//
+                // The format <0 29 4> means the following:
+                //    0 : denotes an SPI interrupt (shared peripheral)
+                //   29 : the kernel adds 32 to this value to get 29+32 = 61
+                //    4 : IRQ_TYPE_LEVEL_HIGH (level sensitive interrupt)
+		//
+		interrupt-parent = <&intc>;
+		interrupts = <0 29 4>,
+		             <0 30 4>,
+		             <0 31 4>,
+		             <0 32 4>;
+	};
+
+	// Reserved memory for DMA buffers
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		puzzlefw {
+			compatible = "jigsaw,puzzlefw";
+			size = <0x4000000>;     // 64 MByte
+			alignment = <0x100000>; //  1 MByte
+			no-map;
+		};
+	};
+
+};
+
+&gem0 {
+	status = "okay";
+	xlnx,ptp-enet-clock = <0x69f6bcb>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	// Red Pitaya: Lantiq Ethernet PHY, MDIO address 1
+	ethernet_phy: ethernet-phy@1 {
+		reg = <1>;
+		device_type = "ethernet-phy";
+	};
+};
+
+&gpio0 {
+	emio-gpio-width = <24>;
+	gpio-mask-high = <0x0>;
+	gpio-mask-low = <0x5600>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	// Red Pitaya: EEPROM chip on internal I2C bus.
+
+	eeprom@50 {
+		compatible = "24c64";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+/*
+	eeprom@51 {
+		compatible = "24c64";
+		reg = <0x51>;
+		pagesize = <32>;
+	};
+*/
+};
+
+&intc {
+	num_cpus = <2>;
+	num_interrupts = <96>;
+};
+
+&qspi {
+	status = "okay";
+	is-dual = <0>;
+	num-cs = <1>;
+	spi-rx-bus-width = <4>;
+	spi-tx-bus-width = <4>;
+};
+
+&sdhci0 {
+	status = "okay";
+	xlnx,has-cd = <0x1>;
+	xlnx,has-power = <0x1>;
+	xlnx,has-wp = <0x1>;
+};
+
+&spi0 {
+	is-decoded-cs = <0>;
+	num-cs = <3>;
+	status = "okay";
+};
+
+&spi1 {
+	is-decoded-cs = <0>;
+	num-cs = <1>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+	device_type = "serial";
+	cts-override;
+};
+
+&uart1 {
+	status = "okay";
+	device_type = "serial";
+	cts-override;
+};
+
+&usb0 {
+	status = "okay";
+	phy_type = "ulpi";
+	dr_mode = "host";
+        usb-phy = <&usb_phy0>;
+	usb-reset = <&gpio0 48 0>;
+};
+
+&clkc {
+	fclk-enable = <0x1>;
+	ps-clk-frequency = <33333333>;
+};
+
+&devcfg {
+	// Override clock list.
+	clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
+	clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
+};
+
+/*
+TODO -- later
+&watchdog0{
+	status = "okay";
+	reset-on-timeout;
+};
+*/
+